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    Searched refs:hclk (Results 1 - 5 of 5) sorted by null

  /external/u-boot/drivers/ddr/marvell/axp/
ddr3_init.c 1143 u32 tmp, hclk; local
1147 hclk = 84;
1160 hclk = 150;
1166 hclk = 165;
1170 hclk = 180;
1177 hclk = 200;
1182 hclk = 222;
1188 hclk = 250;
1194 hclk = 267;
1200 hclk = 300
    [all...]
ddr3_dfs.c 126 u32 hclk; local
128 get_target_freq(cpu_freq, &tmp, &hclk);
632 /* Switch HCLK Mux to training clk (100Mhz), keep DFS request bit */
782 u32 hclk; local
784 get_target_freq(cpu_freq, &tmp, &hclk);
    [all...]
  /external/u-boot/drivers/mtd/nand/
lpc32xx_nand_slc.c 119 uint32_t hclk = get_hclk_clk_rate(); local
134 TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) |
135 TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) |
136 TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) |
138 TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) |
139 TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) |
140 TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP),
  /external/u-boot/arch/arm/mach-s5pc1xx/
clock.c 217 unsigned long hclk; local
236 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
238 return hclk;
  /external/u-boot/arch/arm/dts/
at91sam9261.dtsi 81 clock-names = "ohci_clk", "hclk", "uhpck";
92 clock-names = "lcdc_clk", "hclk";
134 clock-names = "pclk", "hclk";
717 hclk0: hclk@16 {
723 hclk1: hclk@17 {

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