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Searched
refs:hiz
(Results
1 - 6
of
6
) sorted by null
/external/mesa3d/src/mesa/drivers/dri/i965/
gen6_depth_state.c
43
bool
hiz
, bool separate_stencil,
57
/* Enable the
hiz
bit if we're doing separate stencil, because it and the
66
bool enable_hiz_ss =
hiz
|| separate_stencil;
118
((enable_hiz_ss ? 1 : 0) << 22) | /*
hiz
enable */
149
if (
hiz
|| separate_stencil) {
152
* stencil enable' and '
hiz
enable' bits were set. Therefore we must
158
/* Emit
hiz
buffer. */
159
if (
hiz
) {
203
* On Gen >= 6, emit clear params for safety. If using
hiz
, then clear
208
* when
HiZ
is enabled and the DEPTH_BUFFER_STATE changes
[
all
...]
gen8_depth_state.c
45
bool
hiz
,
69
(
hiz
? 1 : 0) << 22 |
85
if (!
hiz
) {
138
bool
hiz
, bool separate_stencil,
209
hiz
, width, height, depth, lod, min_array_element);
240
* 3DSTATE_DEPTH_BUFFER::
HIZ
Enable
255
*
HiZ
operations are done outside of the normal state upload, so they're
gen7_misc_state.c
38
bool
hiz
, bool separate_stencil,
111
((
hiz
? 1 : 0) << 22) |
140
if (!
hiz
) {
brw_misc_state.c
270
bool
hiz
= depth_irb && intel_renderbuffer_has_hiz(depth_irb);
local
301
if ((devinfo->gen < 7 &&
hiz
) || devinfo->gen >= 7) {
305
/* Prior to Gen7, if using separate stencil,
hiz
must be enabled. */
306
assert(devinfo->gen >= 7 || !separate_stencil ||
hiz
);
309
assert(!
hiz
|| depth_mt->surf.tiling == ISL_TILING_Y0);
342
stencil_mt,
hiz
, separate_stencil,
367
bool
hiz
, bool separate_stencil,
371
(void)
hiz
;
375
assert(!
hiz
);
brw_context.h
732
*
HiZ
buffers (i965+ only)
740
bool
hiz
, bool separate_stencil,
[
all
...]
/external/mesa3d/src/intel/isl/
isl_emit_depth_stencil.c
149
struct GENX(3DSTATE_HIER_DEPTH_BUFFER)
hiz
= {
161
hiz
.SurfaceBaseAddress = info->hiz_address;
162
hiz
.HierarchicalDepthBufferMOCS = info->mocs;
163
hiz
.SurfacePitch = info->hiz_surf->row_pitch - 1;
175
* Since depth and
HiZ
buffers are always tiled, they are treated as
178
hiz
.SurfaceQPitch =
215
GENX(3DSTATE_HIER_DEPTH_BUFFER_pack)(NULL, dw, &
hiz
);
Completed in 944 milliseconds