/external/mesa3d/src/mesa/drivers/dri/i965/ |
brw_draw_upload.c | 718 GLuint ib_size; local 728 ib_size = index_buffer->count ? ib_type_size * index_buffer->count : 737 intel_upload_data(brw, index_buffer->ptr, ib_size, ib_type_size, 745 offset, ib_size, false);
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/external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
radv_amdgpu_cs.c | 202 uint32_t ib_size = 20 * 1024 * 4; local 211 cs->ib_buffer = ws->buffer_create(ws, ib_size, 0, 230 cs->base.max_dw = ib_size / 4 - 4; 317 uint64_t ib_size = MAX2(min_size * 4 + 16, cs->base.max_dw * 4 * 2); local 320 ib_size = MIN2(ib_size, 0xfffff); 335 cs->ib_buffer = cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0, 365 cs->base.max_dw = ib_size / 4 - 4; [all...] |
/external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
amdgpu_cs.c | 719 unsigned ib_size = 0; local 724 ib_size = 4 * 1024 * 4; 731 ib_size = MAX2(ib_size, 745 ib->used_ib_space + ib_size > ib->big_ib_buffer->size) { 762 ib_size = ib->big_ib_buffer->size - ib->used_ib_space; 763 ib->base.current.max_dw = ib_size / 4 - amdgpu_cs_epilog_dws(cs->ring_type); [all...] |
/external/mesa3d/src/intel/tools/ |
gen_batch_decoder.c | 381 uint32_t ib_size = 0; local 392 ib_size = iter.raw_value; 402 const void *ib_end = ib.map + MIN2(ib.size, ib_size);
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