/external/u-boot/arch/arm/mach-imx/mx6/ |
clock.c | 24 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; variable in typeref:struct:mxc_ccm_reg 31 reg = __raw_readl(&imx_ccm->CCGR2); 36 __raw_writel(reg, &imx_ccm->CCGR2); 44 clrbits_le32(&imx_ccm->CCGR4, 52 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); 54 clrsetbits_le32(&imx_ccm->cs2cdr, 60 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); 62 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); 64 clrsetbits_le32(&imx_ccm->cs2cdr, 70 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK) 1047 struct mxc_ccm_reg *const imx_ccm local 1074 struct mxc_ccm_reg *const imx_ccm = local 1089 struct mxc_ccm_reg *const imx_ccm = local 1099 struct mxc_ccm_reg *const imx_ccm = local [all...] |
/external/u-boot/arch/arm/mach-imx/mx7/ |
clock_slice.c | 18 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; variable in typeref:struct:mxc_ccm_reg 425 reg = __raw_readl(&imx_ccm->root[clock_id].target_root); 428 __raw_writel(reg, &imx_ccm->root[clock_id].target_root); 443 val = __raw_readl(&imx_ccm->root[clock_id].target_root); 481 reg = __raw_readl(&imx_ccm->root[clock_id].target_root); 484 __raw_writel(reg, &imx_ccm->root[clock_id].target_root); 511 val = __raw_readl(&imx_ccm->root[clock_id].target_root); 540 reg = __raw_readl(&imx_ccm->root[clock_id].target_root); 543 __raw_writel(reg, &imx_ccm->root[clock_id].target_root); 560 val = __raw_readl(&imx_ccm->root[clock_id].target_root) [all...] |
/external/u-boot/arch/arm/mach-imx/ |
cpu.c | 272 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local 275 reg = __raw_readl(&imx_ccm->cbcdr);
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/external/u-boot/board/freescale/mx6sabreauto/ |
mx6sabreauto.c | 263 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local 268 ccgr6 = readl(&imx_ccm->CCGR6); 270 writel(ccgr6, &imx_ccm->CCGR6); 277 cscmr1 = readl(&imx_ccm->cscmr1); 281 writel(cscmr1, &imx_ccm->cscmr1); 285 writel(ccgr6, &imx_ccm->CCGR6);
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