| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) {
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
128 if (Op.isReg()) {
232 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
234 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
237 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
240 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
243 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
246 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) {
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
128 if (Op.isReg()) {
226 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
228 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
231 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
235 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
238 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
241 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 192 return isReg() ? 0 : SubReg_TargetFlags;
195 assert(!isReg() && "Register operands can't have target flags");
200 assert(!isReg() && "Register operands can't have target flags");
229 /// isReg - Tests if this is a MO_Register operand.
230 bool isReg() const { return OpKind == MO_Register; }
268 assert(isReg() && "This is not a register operand!");
273 assert(isReg() && "Wrong MachineOperand accessor");
278 assert(isReg() && "Wrong MachineOperand accessor");
283 assert(isReg() && "Wrong MachineOperand accessor");
288 assert(isReg() && "Wrong MachineOperand accessor")
[all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| AArch64GenAsmWriter.inc | [all...] |
| AArch64GenAsmWriter1.inc | [all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| MachineOperand.h | 190 /// isReg - Tests if this is a MO_Register operand.
191 bool isReg() const { return OpKind == MO_Register; }
222 assert(isReg() && "This is not a register operand!");
227 assert(isReg() && "Wrong MachineOperand accessor");
232 assert(isReg() && "Wrong MachineOperand accessor");
237 assert(isReg() && "Wrong MachineOperand accessor");
242 assert(isReg() && "Wrong MachineOperand accessor");
247 assert(isReg() && "Wrong MachineOperand accessor");
252 assert(isReg() && "Wrong MachineOperand accessor");
257 assert(isReg() && "Wrong MachineOperand accessor")
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 216 return isReg() ? 0 : SubReg_TargetFlags;
219 assert(!isReg() && "Register operands can't have target flags");
224 assert(!isReg() && "Register operands can't have target flags");
310 /// isReg - Tests if this is a MO_Register operand.
311 bool isReg() const { return OpKind == MO_Register; }
350 assert(isReg() && "This is not a register operand!");
355 assert(isReg() && "Wrong MachineOperand accessor");
360 assert(isReg() && "Wrong MachineOperand accessor");
365 assert(isReg() && "Wrong MachineOperand accessor");
370 assert(isReg() && "Wrong MachineOperand accessor")
[all...] |
| /external/capstone/arch/Mips/ |
| MipsInstPrinter.c | 105 static bool isReg(MCInst *MI, unsigned OpNo, unsigned R)
346 if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
348 if (isReg(MI, 1, Mips_ZERO))
353 if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
358 if (isReg(MI, 1, Mips_ZERO_64))
363 if (isReg(MI, 1, Mips_ZERO))
368 if (isReg(MI, 1, Mips_ZERO))
373 if (isReg(MI, 1, Mips_ZERO_64)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| MipsGenAsmWriter.inc | [all...] |
| /external/llvm/lib/CodeGen/ |
| AntiDepBreaker.h | 60 if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == OldReg)
|
| LivePhysRegs.cpp | 48 if (O->isReg()) {
61 if (!O->isReg() || !O->readsReg())
78 if (O->isReg()) {
99 if (Reg.second->isReg() && Reg.second->isDead())
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| AntiDepBreaker.h | 64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| MachineLocation.h | 47 bool isReg() const { return IsRegister; }
|
| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiMCCodeEmitter.cpp | 115 if (MCOp.isReg())
149 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))
153 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
157 (Op2.isReg() && Op2.getReg() != Lanai::R0)))
196 assert(Op1.isReg() && "First operand is not register.");
228 assert(Op1.isReg() && "First operand is not register.");
230 assert(Op2.isReg() && "Second operand is not register.");
267 assert(Op1.isReg() && "First operand is not register.");
295 if (MCOp.isReg() || MCOp.isImm()
[all...] |
| /external/llvm/lib/MC/ |
| MCInstrDesc.cpp | 47 if (MI.getOperand(i).isReg() &&
66 if (MI.getOperand(i).isReg() &&
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| InstructionSelector.cpp | 52 if (MO.isReg() && MO.getReg())
60 if (!Root.isReg())
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/ |
| MCInstrDesc.cpp | 47 if (MI.getOperand(i).isReg() &&
66 if (MI.getOperand(i).isReg() &&
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIFoldOperands.cpp | 62 assert(FoldOp->isReg());
103 assert(Old.isReg());
175 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() ||
176 !MI->getOperand(CommuteIdx1).isReg()))
200 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) ||
323 if (!FoldingImm && !OpToFold.isReg())
333 if (OpToFold.isReg() &&
344 if (Dst.isReg() &&
372 assert(Fold.OpToFold && Fold.OpToFold->isReg());
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiMCCodeEmitter.cpp | 113 if (MCOp.isReg())
147 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))
151 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
155 (Op2.isReg() && Op2.getReg() != Lanai::R0)))
194 assert(Op1.isReg() && "First operand is not register.");
226 assert(Op1.isReg() && "First operand is not register.");
228 assert(Op2.isReg() && "Second operand is not register.");
265 assert(Op1.isReg() && "First operand is not register.");
293 if (MCOp.isReg() || MCOp.isImm()
[all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 157 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
195 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
220 assert(MI.getOperand(OpNo+1).isReg());
239 assert(MI.getOperand(OpNo+1).isReg());
257 assert(MI.getOperand(OpNo+1).isReg());
272 assert(MI.getOperand(OpNo+1).isReg());
288 assert(MI.getOperand(OpNo+1).isReg());
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 164 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
176 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
189 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
202 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
214 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
227 assert(MI.getOperand(OpNo+1).isReg());
245 assert(MI.getOperand(OpNo+1).isReg());
263 assert(MI.getOperand(OpNo+1).isReg());
279 assert(MI.getOperand(OpNo+1).isReg());
294 assert(MI.getOperand(OpNo+1).isReg());
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 89 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
100 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
111 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
122 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
134 assert(MI.getOperand(OpNo+1).isReg());
152 assert(MI.getOperand(OpNo+1).isReg());
179 if (MO.isReg()) {
|
| /external/llvm/include/llvm/MC/MCParser/ |
| MCParsedAsmOperand.h | 58 /// isReg - Is this a register operand?
59 virtual bool isReg() const = 0;
|
| /external/llvm/include/llvm/MC/ |
| MachineLocation.h | 53 bool isReg() const { return IsRegister; }
|
| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| SparcInstPrinter.cpp | 63 if (!MI->getOperand(0).isReg())
87 || (!MI->getOperand(0).isReg())
113 if (MO.isReg()) {
153 if (MO.isReg() && MO.getReg() == SP::G0)
|
