| /external/llvm/lib/Target/AMDGPU/ |
| SIShrinkInstructions.cpp | 69 static bool isVGPR(const MachineOperand *MO, const SIRegisterInfo &TRI,
96 if (!isVGPR(Src2, TRI, MRI) ||
110 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0)))
150 if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI))
|
| GCNHazardRecognizer.cpp | 238 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
256 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
|
| SIRegisterInfo.h | 193 bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
|
| SIRegisterInfo.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIFixWWMLiveness.cpp | 123 if (TRI->isVGPR(*MRI, Reg))
|
| SIShrinkInstructions.cpp | 87 if (!Src1->isReg() || !TRI.isVGPR(MRI, Src1->getReg()))
95 if (!Src2->isReg() || !TRI.isVGPR(MRI, Src2->getReg()) ||
106 if (Src1 && (!Src1->isReg() || !TRI.isVGPR(MRI, Src1->getReg()) ||
|
| GCNHazardRecognizer.cpp | 413 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
434 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
544 if (!TRI->isVGPR(MRI, Def.getReg()))
651 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
|
| SIRegisterInfo.h | 197 bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
|
| SIInsertWaitcnts.cpp | 492 if (TRI->isVGPR(MRIA, Op.getReg())) {
523 assert(TRI->isVGPR(*MRI, Opnd.getReg()));
585 if (Op.isReg() && !Op.isDef() && TRI->isVGPR(MRIA, Op.getReg())) {
633 TRI->isVGPR(MRIA, DefMO.getReg())) {
641 if (MO.isReg() && !MO.isDef() && TRI->isVGPR(MRIA, MO.getReg())) {
[all...] |
| SIInsertSkips.cpp | 248 if (TRI->isVGPR(MBB.getParent()->getRegInfo(),
|
| SIInstrInfo.cpp | [all...] |
| SIPeepholeSDWA.cpp | [all...] |
| SIRegisterInfo.cpp | [all...] |
| SIISelLowering.cpp | [all...] |
