HomeSort by relevance Sort by last modified time
    Searched refs:l2actlr (Results 1 - 3 of 3) sorted by null

  /external/u-boot/arch/arm/cpu/armv7/
cp15.c 17 void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr,
21 asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr));
start.S 218 isb @ Recommended ISB after l2actlr update
  /external/u-boot/arch/arm/mach-omap2/omap5/
hwinit.c 323 u32 l2actlr; local
325 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
327 * L2ACTLR: Ensure to enable the following:
332 l2actlr |= 0x118;
333 omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);

Completed in 795 milliseconds