| /external/u-boot/drivers/net/phy/ |
| et1011c.c | 43 int mii_reg; local
46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG);
48 if (mii_reg & ET1011C_DUPLEX_STATUS)
53 speed = mii_reg & ET1011C_SPEED_MASK;
57 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG);
58 mii_reg &= ~ET1011C_TX_FIFO_MASK;
60 mii_reg |
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| natsemi.c | 65 int mii_reg; local
67 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR);
69 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
85 if (mii_reg & MIIM_DP83865_DPX_FULL)
118 int mii_reg; local
120 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
122 if(mii_reg & (BMSR_100FULL | BMSR_100HALF)) {
128 if (mii_reg & (BMSR_10FULL | BMSR_100FULL)) {
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| davicom.c | 43 int mii_reg; local
45 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR);
47 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
52 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
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| realtek.c | 161 unsigned int mii_reg; local
163 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS);
165 if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
171 while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
182 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
188 if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK)
194 if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX)
199 speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED);
218 unsigned int mii_reg; local
222 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PHY_STATUS)
[all...] |
| smsc.c | 17 int mii_reg; local
19 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
21 if (mii_reg & (BMSR_100FULL | BMSR_100HALF))
26 if (mii_reg & (BMSR_10FULL | BMSR_100FULL))
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| lxt.c | 22 int mii_reg; local
25 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_LXT971_SR2);
26 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
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| phy.c | 224 unsigned int mii_reg; local
230 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
236 if (phydev->link && mii_reg & BMSR_LSTATUS)
240 !(mii_reg & BMSR_ANEGCOMPLETE)) {
245 while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
265 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
271 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
273 if (mii_reg & BMSR_LSTATUS)
293 int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); local
355 if ((mii_reg & BMSR_ESTATEN) && !(mii_reg & BMSR_ERCAP)
[all...] |
| marvell.c | 156 unsigned int mii_reg; local
158 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
160 if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
161 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
165 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
176 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
182 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
188 if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
193 speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
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| vitesse.c | 87 int mii_reg; local
89 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT);
91 if (mii_reg & MIIM_CIS82xx_AUXCONSTAT_DUPLEX)
96 speed = mii_reg & MIIM_CIS82xx_AUXCONSTAT_SPEED;
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| broadcom.c | 67 unsigned int mii_reg; local
69 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS);
71 switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>
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| mscc.c | 202 u16 mii_reg; local
204 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_AUX_CNTRL_STAT_REG);
206 if (mii_reg & MIIM_AUX_CNTRL_STAT_F_DUPLEX)
211 speed = mii_reg & MIIM_AUX_CNTRL_STAT_SPEED_MASK;
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| mv88e61xx.c | 462 unsigned int mii_reg; local
464 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
466 if ((mii_reg & PHY_REG_STATUS1_LINK) &&
467 !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
471 while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
482 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
488 if (mii_reg & PHY_REG_STATUS1_LINK)
494 if (mii_reg & PHY_REG_STATUS1_DUPLEX)
499 speed = mii_reg & PHY_REG_STATUS1_SPEED;
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| /external/u-boot/drivers/net/ |
| smc91111.c | 887 word mii_reg; local
951 mii_reg = SMC_inw (dev, MII_REG);
954 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
959 SMC_outw (dev, mii_reg | bits[i], MII_REG);
964 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
966 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
971 SMC_outw (dev, mii_reg, MII_REG)
1005 word mii_reg; local
[all...] |
| /external/u-boot/drivers/qe/ |
| uec_phy.c | 130 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; local
151 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
169 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; local
189 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
207 ("read wrong value : mii_id %d,mii_reg %d, base %08x",
208 mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
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