/bionic/libc/arch-arm/bionic/ |
__aeabi_read_tp.S | 46 mrc p15, 0, r0, c13, c0, 3
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vfork.S | 35 mrc p15, 0, r3, c13, c0, 3
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/device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ |
ArmCortexA9Helper.S | 22 mrc p15, 4, r0, c15, c0, 0
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/external/u-boot/arch/x86/cpu/quark/ |
Makefile | 6 obj-y += mrc.o mrc_util.o hte.o smc.o
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/external/u-boot/arch/arm/cpu/armv7/ |
sctlr.S | 18 mrc p15, 0, r0, c1, c0, 0 @ load system control register
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start.S | 46 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 71 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register 153 mrc p15, 0, r0, c1, c0, 0 166 mrc p15, 0, r0, c1, c0, 0 @ read system control register 172 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 178 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 184 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 189 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 195 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 201 mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR [all...] |
/external/u-boot/arch/arm/mach-rmobile/ |
lowlevel_init_ca15.S | 14 mrc p15, 0, r4, c0, c0, 5 /* mpidr */ 52 mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */ 58 mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */ 72 mrc p15, 0, r0, c1, c0, 1
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/external/u-boot/arch/arm/cpu/armv7/sunxi/ |
fel_utils.S | 19 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register 21 mrc p15, 0, lr, c12, c0, 0 @ Read VBAR 23 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
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/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Arm/ |
ArmLibSupport.S | 20 mrc p15,0,R0,c0,c0,0
24 mrc p15,0,R0,c0,c0,1
63 mrc p15, 0, r0, c1, c0, 2
76 mrc p15, 0, r0, c1, c0, 1
90 mrc p15,0,r0,c2,c0,0
120 mrc p15, 0, r0, c1, c1, 0
129 mrc p15, 4, r0, c12, c0, 0
137 mrc p15, 0, r0, c12, c0, 1
153 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
157 mrc p15, 0, r0, c1, c0, 1 [all...] |
ArmLibSupportV7.S | 20 mrc p15,0,R0,c0,c0,5
76 mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
84 mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
88 mrc p15, 0, r0, c1, c1, 2
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ArmV7Support.S | 71 mrc p15,0,R0,c1,c0,0
80 mrc p15,0,R0,c1,c0,0
91 mrc p15, 0, r0, c1, c0, 0 @ Get control register
101 mrc p15,0,R0,c1,c0,0
107 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
116 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
125 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
134 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
142 mrc p15, 0, r0, c1, c0, 0
149 mrc p15, 0, r0, c1, c0, 0 [all...] |
ArmV7Support.asm | 74 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
82 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
93 mrc p15, 0, r0, c1, c0, 0 ; Get control register
103 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
109 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
118 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
127 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
136 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
143 mrc p15, 0, r0, c1, c0, 0
150 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) [all...] |
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
MemoryInitPei.inf | 56 mrc.h
57 mrc.c
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/external/u-boot/arch/arm/cpu/arm926ejs/spear/ |
start.S | 70 mrc p15, 0, r0, c1, c0, 0
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/external/u-boot/arch/arm/include/asm/arch-armv7/ |
generictimer.h | 40 mrc p15, 0, \reg, c14, c2, 1
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/external/u-boot/arch/arm/mach-zynq/ |
lowlevel_init.S | 13 mrc p15, 0, r1, c1, c0, 2
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/device/linaro/bootloader/edk2/ArmPkg/Library/ArmMmuLib/Arm/ |
ArmMmuLibV7Support.S | 26 mrc p15,0,R0,c0,c0,5
32 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 Register
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/external/icu/android_icu4j/src/main/java/android/icu/impl/ |
ICURWLock.java | 79 private Stats(int rc, int mrc, int wrc, int wc, int wwc) { 81 this._mrc = mrc; 97 " mrc: " + _mrc +
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/external/icu/icu4j/main/classes/core/src/com/ibm/icu/impl/ |
ICURWLock.java | 76 private Stats(int rc, int mrc, int wrc, int wc, int wwc) { 78 this._mrc = mrc; 94 " mrc: " + _mrc +
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/external/u-boot/arch/arm/cpu/arm926ejs/ |
start.S | 79 mrc p15, 0, r15, c7, c10, 3 89 mrc p15, 0, r0, c1, c0, 0
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/external/u-boot/arch/arm/mach-uniphier/arm32/ |
psci_smp.S | 14 mrc p15, 0, r1, c1, c0, 0 @ SCTLR (System Control Register) 26 mrc p15, 0, r1, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
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/external/u-boot/arch/x86/cpu/intel_common/ |
Makefile | 9 obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += mrc.o
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/external/tcpdump/ |
print-igmp.c | 207 u_int mrc; local 219 mrc = bp[1]; 220 if (mrc < 128) { 221 mrt = mrc; 223 mrt = ((mrc & 0x0f) | 0x10) << (((mrc & 0x70) >> 4) + 3); 225 if (mrc != 100) {
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/device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/GicV3/Arm/ |
ArmGicV3.S | 25 mrc p15, 0, r0, c12, c12, 5 // ICC_SRE
69 mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1
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/external/u-boot/arch/arm/cpu/arm926ejs/mxs/ |
start.S | 63 mrc p15, 0, r2, c1, c0, 0
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