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  /external/u-boot/arch/arm/mach-exynos/
dmc_init_ddr3.c 803 dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1));
811 writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1);
  /external/u-boot/arch/arm/mach-exynos/include/mach/
power.h 291 unsigned int pmu_spare1; member in struct:exynos5_power
915 unsigned int pmu_spare1; /* Store PHY0_CON4 for read leveling */ member in struct:exynos5420_power
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