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Searched
refs:pmu_spare2
(Results
1 - 2
of
2
) sorted by null
/external/u-boot/arch/arm/mach-exynos/
dmc_init_ddr3.c
804
dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->
pmu_spare2
));
812
writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->
pmu_spare2
);
/external/u-boot/arch/arm/mach-exynos/include/mach/
power.h
292
unsigned int
pmu_spare2
;
member in struct:exynos5_power
916
unsigned int
pmu_spare2
; /* Store PHY1_CON4 for read leveling */
member in struct:exynos5420_power
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