| /external/u-boot/drivers/clk/rockchip/ |
| clk_rk3128.c | 32 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
50 div->postdiv2, vco_hz, output_hz);
63 (div->postdiv2 << PLL_POSTDIV2_SHIFT |
79 u32 postdiv1, postdiv2 = 1; local
94 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
95 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
98 vco_khz = freq_khz * postdiv1 * postdiv2;
101 postdiv2 > max_postdiv2) {
108 div->postdiv2 = postdiv2
241 u32 refdiv, fbdiv, postdiv1, postdiv2; local
[all...] |
| clk_rk3036.c | 34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
52 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
54 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\
57 div->postdiv2, vco_hz, output_hz);
68 (div->postdiv2 << PLL_POSTDIV2_SHIFT |
172 uint32_t refdiv, fbdiv, postdiv1, postdiv2; local
201 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
203 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
|
| clk_rk3399.c | 36 u32 postdiv2; member in struct:pll_div
47 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
281 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
295 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
298 "postdiv2=%d, vco=%u khz, output=%u khz\n",
300 div->postdiv2, vco_khz, output_khz);
321 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
337 u32 postdiv1, postdiv2 = 1; local
352 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
353 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
[all...] |
| clk_rv1108.c | 32 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
63 uint32_t refdiv, fbdiv, postdiv1, postdiv2; local
76 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT;
78 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
|
| clk_rk322x.c | 31 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
49 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
53 div->postdiv2, vco_hz, output_hz);
66 (div->postdiv2 << PLL_POSTDIV2_SHIFT |
173 uint32_t refdiv, fbdiv, postdiv1, postdiv2; local
202 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
204 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
321 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
325 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
329 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}
[all...] |
| clk_rk3328.c | 24 u32 postdiv2; member in struct:pll_div
35 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
196 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
242 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
245 postdiv2=%d, vco=%u khz, output=%u khz\n",
247 div->postdiv2, vco_khz, output_khz);
268 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
|
| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| cru_rv1108.h | 53 u32 postdiv2; member in struct:pll_div
|
| cru_rk3036.h | 64 u32 postdiv2; member in struct:pll_div
|
| cru_rk3128.h | 67 u32 postdiv2; member in struct:pll_div
|
| cru_rk322x.h | 65 u32 postdiv2; member in struct:pll_div
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/ |
| dfs.c | 27 {.mhz = 928, .refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1},
28 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1},
29 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1},
30 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1},
31 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1},
32 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1},
33 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1},
34 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1},
35 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2},
1710 uint32_t refdiv, postdiv1, fbdiv, postdiv2; local
[all...] |
| suspend.c | 665 uint32_t refdiv, postdiv2, postdiv1, fbdiv; local
678 postdiv2 = POSTDIV2_DEC(dpll_data[1]);
683 (refdiv * postdiv1 * postdiv2)) * MHz;
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/ |
| soc.h | 30 #define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12))
128 uint32_t postdiv2; member in struct:pll_div
|
| /external/u-boot/arch/arm/mach-rockchip/rk3036/ |
| sdram_rk3036.c | 38 * refdiv, fbdiv, postdiv1, postdiv2
343 (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
|
