| /external/u-boot/drivers/ddr/marvell/a38x/ |
| ddr3_training_ip_engine.h | 43 u32 pup_num, u32 bit_num,
54 u32 pup_num, enum hws_training_result result_type,
65 u32 pup_num,
|
| ddr3_training_ip_engine.c | 337 u32 pup_num, enum hws_training_result result_type,
358 if (pup_num >= octets_per_if_num) {
360 ("pup_num %d not valid\n", pup_num));
423 reg_data |= pup_num << 14;
692 u32 pup_num, u32 bit_num,
722 ("Read_from_d_b %d cs_type %d oper %d result_type %d direction %d search %d pup_num %d if_id %d pup_access_type %d\n",
724 result_type, direction, search, pup_num,
732 if (pup_num >= octets_per_if_num) {
734 ("pup_num %d not valid\n", pup_num))
[all...] |
| /external/u-boot/drivers/ddr/marvell/axp/ |
| ddr3_write_leveling.c | 186 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; local
294 pup_num = (ecc) ? ECC_PUP : pup;
308 DEBUG_WL_D((u32) pup_num, 1);
339 [pup_num]
346 [pup_num][P] +
350 [pup_num]
354 [cs][pup_num]
366 [cs][pup_num]
370 [cs][pup_num]
383 [pup_num]
474 u32 reg, phase, delay, cs, pup, pup_num; local
1127 u32 reg, pup_num, delay, phase, phaseMax, max_pup_num, pup, local
[all...] |
| ddr3_dqs.c | 1264 u32 pup, pup_num; local
[all...] |
| ddr3_read_leveling.c | 181 u32 reg, cs, ecc, pup_num, phase, delay, pup; local
287 pup_num = (pup == dram_info->num_of_std_pups) ? ECC_BIT : pup;
292 ddr3_write_pup_reg(PUP_RL_MODE, cs, pup_num, phase,
465 /* pup_num = Q or 1 for ECC */
577 /* pup_num = Q or 1 for ECC */
605 /* pup_num = Q or 1 for ECC */
821 /* pup_num = Q or 1 for ECC */
[all...] |
