/device/linaro/bootloader/arm-trusted-firmware/include/plat/arm/css/common/ |
css_pm.h | 18 #define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0] 19 #define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1] 22 (state)->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] : 0)
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/device/linaro/bootloader/arm-trusted-firmware/plat/arm/board/fvp/ |
fvp_pm.c | 86 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 93 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 110 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == 166 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 184 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 202 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 206 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 225 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 230 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == 266 if (target_state->pwr_domain_state[ARM_PWR_LVL0] = [all...] |
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/ |
plat_psci_handlers.c | 45 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; 54 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 55 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; 64 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 66 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = 115 const plat_local_state_t *pwr_domain_state = local 116 target_state->pwr_domain_state; 117 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; 118 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; 119 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] [all...] |
/device/linaro/bootloader/arm-trusted-firmware/plat/xilinx/zynqmp/ |
plat_psci.c | 94 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 95 __func__, i, target_state->pwr_domain_state[i]); 112 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 113 __func__, i, target_state->pwr_domain_state[i]); 135 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 136 __func__, i, target_state->pwr_domain_state[i]); 163 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 164 __func__, i, target_state->pwr_domain_state[i]); 166 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? 173 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) [all...] |
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/ |
plat_psci_handlers.c | 72 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; 73 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 87 const plat_local_state_t *pwr_domain_state; local 96 pwr_domain_state = target_state->pwr_domain_state; 97 stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & 99 stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & 234 const plat_local_state_t *pwr_domain_state = local 235 target_state->pwr_domain_state; 237 unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] [all...] |
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/common/ |
plat_pm.c | 19 ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 21 ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 23 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 150 req_state->pwr_domain_state[MPIDR_AFFLVL0] = 154 req_state->pwr_domain_state[i] = 158 req_state->pwr_domain_state[i] = 174 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 229 lvl_state = target_state->pwr_domain_state[lvl]; 265 lvl_state = target_state->pwr_domain_state[lvl]; 286 lvl_state = target_state->pwr_domain_state[lvl] [all...] |
/device/linaro/bootloader/arm-trusted-firmware/plat/compat/ |
plat_pm_compat.c | 38 * 'pwr_domain_state' for each power level. It is assumed that, when in 64 req_state->pwr_domain_state[0] = 68 req_state->pwr_domain_state[i] = 184 target_state->pwr_domain_state[level]) ? 200 target_state->pwr_domain_state[level]) ? 217 target_state->pwr_domain_state[level]) ? 235 target_state->pwr_domain_state[level]) ?
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/device/linaro/bootloader/arm-trusted-firmware/plat/arm/common/ |
arm_pm.c | 54 req_state->pwr_domain_state[ARM_PWR_LVL0] = 58 req_state->pwr_domain_state[i] = 104 req_state->pwr_domain_state[i++] = state_id &
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/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/ |
plat_psci_handlers.c | 53 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 56 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = 128 write_actlr_el1(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]);
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/device/linaro/bootloader/arm-trusted-firmware/plat/arm/css/drivers/scp/ |
css_pm_scmi.c | 91 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 112 assert(target_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] == 120 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) 123 assert(target_state->pwr_domain_state[lvl] == 156 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 160 assert(target_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] == 164 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) 167 assert(target_state->pwr_domain_state[lvl] ==
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/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/ |
plat_pm.c | 35 #define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0] 36 #define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1] 38 (state)->pwr_domain_state[MTK_PWR_LVL2] : 0) 557 assert(state->pwr_domain_state[MPIDR_AFFLVL0] == MTK_LOCAL_STATE_OFF); 560 (state->pwr_domain_state[MTK_PWR_LVL2] == MTK_LOCAL_STATE_OFF)) 563 if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) { 569 (state->pwr_domain_state[MTK_PWR_LVL2] == MTK_LOCAL_STATE_OFF)) 619 if (state->pwr_domain_state[MTK_PWR_LVL0] == MTK_LOCAL_STATE_RET) 659 req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF; 716 req_state->pwr_domain_state[MTK_PWR_LVL0] [all...] |
/device/linaro/bootloader/arm-trusted-firmware/lib/psci/ |
psci_stat.c | 85 if (is_local_state_run(state_info->pwr_domain_state[lvl])) 116 local_state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; 133 local_state = state_info->pwr_domain_state[lvl]; 196 local_state = state_info.pwr_domain_state[pwrlvl];
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psci_common.c | 288 plat_local_state_t *pd_state = target_state->pwr_domain_state; 301 target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; 314 const plat_local_state_t *pd_state = target_state->pwr_domain_state; 413 state_info->pwr_domain_state[lvl]); 428 state_info->pwr_domain_state[lvl] = target_state; 431 if (is_local_state_run(state_info->pwr_domain_state[lvl])) 445 state_info->pwr_domain_state[lvl]); 446 state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; 482 state = state_info->pwr_domain_state[i]; 526 if (is_local_state_off(state_info->pwr_domain_state[i]) [all...] |
psci_off.c | 25 state_info->pwr_domain_state[lvl] = PLAT_MAX_OFF_STATE;
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psci_suspend.c | 281 state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]));
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psci_main.c | 92 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; 173 assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]));
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/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/poplar/ |
plat_pm.c | 76 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == 120 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 122 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 148 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/ |
tegra_pm.c | 117 req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN; 171 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 186 uint8_t pwr_state = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; 231 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
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/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/ |
hikey_pm.c | 23 ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 25 ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 27 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 167 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 234 req_state->pwr_domain_state[MPIDR_AFFLVL0] = 238 req_state->pwr_domain_state[i] =
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/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/ |
hikey960_pm.c | 23 ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 25 ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 27 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 145 req_state->pwr_domain_state[MPIDR_AFFLVL0] = 149 req_state->pwr_domain_state[i] = 280 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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/device/linaro/bootloader/arm-trusted-firmware/plat/qemu/ |
qemu_pm.c | 90 req_state->pwr_domain_state[i++] = state_id & 171 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
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/device/linaro/bootloader/arm-trusted-firmware/plat/arm/css/common/ |
css_pm.c | 244 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; 271 req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] = ARM_LOCAL_STATE_RUN;
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/device/linaro/bootloader/arm-trusted-firmware/plat/common/ |
plat_psci_common.c | 105 state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL];
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/device/linaro/bootloader/arm-trusted-firmware/include/lib/psci/ |
psci.h | 250 * The pwr_domain_state[] stores the local power state at each level 253 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)]; member in struct:psci_power_state 298 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state,
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