| /external/u-boot/arch/arm/dts/ |
| stm32f429.dtsi | 47 #include <dt-bindings/mfd/stm32f4-rcc.h>
81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
90 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
110 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
119 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
148 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
168 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
176 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
196 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>
[all...] |
| stm32h743.dtsi | 46 #include <dt-bindings/mfd/stm32h7-rcc.h>
70 rcc: rcc@58024400 {
73 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
84 clocks = <&rcc USART1_CK>;
92 clocks = <&rcc USART2_CK>;
99 clocks = <&rcc TIM5_CK>;
110 clocks = <&rcc FMC_CK>;
129 clocks = <&rcc SDMMC1_CK>
[all...] |
| stm32f746.dtsi | 51 #include <dt-bindings/mfd/stm32f7-rcc.h>
68 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
69 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
70 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
82 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
94 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
95 resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
102 clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
112 rcc: rcc@40023810
[all...] |
| stm32h743-pinctrl.dtsi | 59 clocks = <&rcc GPIOA_CK>;
68 clocks = <&rcc GPIOB_CK>;
77 clocks = <&rcc GPIOC_CK>;
86 clocks = <&rcc GPIOD_CK>;
95 clocks = <&rcc GPIOE_CK>;
104 clocks = <&rcc GPIOF_CK>;
113 clocks = <&rcc GPIOG_CK>;
122 clocks = <&rcc GPIOH_CK>;
131 clocks = <&rcc GPIOI_CK>;
140 clocks = <&rcc GPIOJ_CK>
[all...] |
| stm32f4-pinctrl.dtsi | 45 #include <dt-bindings/mfd/stm32f4-rcc.h>
63 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
73 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
83 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
93 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
103 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
113 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
123 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
133 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
143 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>
[all...] |
| stm32f429-disco.dts | 107 assigned-clocks = <&rcc 1 CLK_RTC>;
108 assigned-clock-parents = <&rcc 1 CLK_LSI>;
|
| stm32mp157.dtsi | 103 rcc: rcc@50000000 {
108 rcc_clk: rcc-clk@50000000 {
110 compatible = "st,stm32mp1-rcc-clk";
113 rcc_rst: rcc-reset@50000000 {
115 compatible = "st,stm32mp1-rcc-rst";
118 rcc_reboot: rcc-reboot@50000000 {
120 regmap = <&rcc>;
131 st,sysrcc = <&rcc>;
137 st,tzcr = <&rcc 0x0 0x1>
[all...] |
| stm32f469-disco.dts | 85 &rcc {
86 compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc";
|
| /external/u-boot/drivers/clk/ |
| clk_stm32mp1.c | 38 /* RCC registers */
1105 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1108 u32 address = rcc + offset;
1116 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1119 setbits_le32(rcc + RCC_OCENSETR, mask_on);
1121 setbits_le32(rcc + RCC_OCENCLRR, mask_on);
1124 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1128 u32 address = rcc + offset;
1146 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
1151 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP)
1301 fdt_addr_t rcc = priv->base; local
1317 fdt_addr_t rcc = priv->base; local
1498 fdt_addr_t rcc = priv->base; local
[all...] |
| clk_stm32f.c | 16 #include <dt-bindings/mfd/stm32f7-rcc.h>
79 * RCC AHB1ENR specific definitions
86 * RCC APB1ENR specific definitions
92 * RCC APB2ENR specific definitions
151 /* Reset RCC configuration */
|
| /external/u-boot/drivers/ram/stm32mp1/ |
| stm32mp1_ddr.c | 383 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
384 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
385 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
386 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
387 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
388 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
397 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
398 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
402 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
428 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST)
[all...] |
| stm32mp1_ddr.h | 29 * @rcc: rcc base address
37 u32 rcc; member in struct:ddr_info
|
| stm32mp1_ram.c | 46 debug("DDR: mem_speed (%d MHz), RCC %d MHz\n",
156 priv->rcc = STM32_RCC_BASE;
|
| /cts/tests/tests/media/src/android/media/cts/ |
| MediaRouterTest.java | 225 RemoteControlClient rcc = new RemoteControlClient(mediaButtonIntent); local
226 userRoute.setRemoteControlClient(rcc);
227 assertEquals(rcc, userRoute.getRemoteControlClient());
|
