| /external/u-boot/arch/arm/mach-rockchip/rk3288/ |
| rk3288.c | 15 rk_setreg(GRF_SOC_CON2, 1 << 0);
|
| /external/u-boot/arch/arm/mach-rockchip/ |
| rk3368-board-tpl.c | 54 rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
55 rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
56 rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
67 rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
68 rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
72 rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
73 rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
|
| rk3288-board.c | 334 rk_setreg(GRF_SOC_CON2, 1 << 0);
|
| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| hardware.h | 18 #define rk_setreg(addr, set) writel((set) << 16 | (set), addr) macro
|
| /external/u-boot/drivers/video/rockchip/ |
| rk3288_vop.c | 40 rk_setreg(&grf->io_vsel, 1 << 0);
|
| rk3288_hdmi.c | 31 rk_setreg(&grf->soc_con6, 1 << 15);
|
| rk_lvds.c | 70 rk_setreg(&priv->grf->soc_con6, val);
81 rk_setreg(&priv->grf->soc_con7, val);
|
| rk_edp.c | 1058 rk_setreg(&priv->grf->soc_con12, 1 << 4);
1061 rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : (1 << 5));
|
| /external/u-boot/drivers/reset/ |
| reset-rockchip.c | 57 rk_setreg(priv->base + (bank * 4), BIT(offset));
|
| /external/u-boot/board/theobroma-systems/puma_rk3399/ |
| puma-rk3399.c | 196 rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT);
|
| /external/u-boot/drivers/clk/rockchip/ |
| clk_rk3128.c | 55 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
57 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
380 rk_setreg(&cru->cru_clksel_con[10],
|
| clk_rk3288.c | 159 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
781 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
784 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
817 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
|
| clk_rk322x.c | 58 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
60 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
|
| clk_rk3328.c | 684 rk_setreg(&grf->mac_con[1], BIT(10));
721 rk_setreg(&grf->soc_con[4], BIT(14));
|
| clk_rk3036.c | 62 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
|
| clk_rk3188.c | 101 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
|
| clk_rk3368.c | 551 rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
|
| clk_rk3399.c | 971 rk_setreg(&priv->cru->clksel_con[19], BIT(4));
[all...] |
| /external/u-boot/drivers/ram/rockchip/ |
| dmc-rk3368.c | 141 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
149 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
342 rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
|
| sdram_rk3288.c | 443 rk_setreg(&grf->soc_con0, 1 << (8 + channel));
|
| /external/u-boot/arch/arm/mach-rockchip/rk3036/ |
| sdram_rk3036.c | 336 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
|
