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  /external/u-boot/arch/arm/mach-exynos/
clock_init.h 78 unsigned rpll_pdiv; member in struct:mem_timings
clock_init_exynos5.c 181 .rpll_pdiv = 0x2,
804 writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
906 val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);

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