| /external/llvm/test/MC/AArch64/ |
| neon-3vdiff.s | 409 rsubhn2 v0.16b, v1.8h, v2.8h
410 rsubhn2 v0.8h, v1.4s, v2.4s
411 rsubhn2 v0.4s, v1.2d, v2.2d
413 // CHECK: rsubhn2 v0.16b, v1.8h, v2.8h // encoding: [0x20,0x60,0x22,0x6e]
414 // CHECK: rsubhn2 v0.8h, v1.4s, v2.4s // encoding: [0x20,0x60,0x62,0x6e]
415 // CHECK: rsubhn2 v0.4s, v1.2d, v2.2d // encoding: [0x20,0x60,0xa2,0x6e]
|
| neon-diagnostics.s | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| neon-3vdiff.s | 409 rsubhn2 v0.16b, v1.8h, v2.8h
410 rsubhn2 v0.8h, v1.4s, v2.4s
411 rsubhn2 v0.4s, v1.2d, v2.2d
413 // CHECK: rsubhn2 v0.16b, v1.8h, v2.8h // encoding: [0x20,0x60,0x22,0x6e]
414 // CHECK: rsubhn2 v0.8h, v1.4s, v2.4s // encoding: [0x20,0x60,0x62,0x6e]
415 // CHECK: rsubhn2 v0.4s, v1.2d, v2.2d // encoding: [0x20,0x60,0xa2,0x6e]
|
| neon-diagnostics.s | [all...] |
| /external/capstone/suite/MC/AArch64/ |
| neon-3vdiff.s.cs | 141 0x20,0x60,0x22,0x6e = rsubhn2 v0.16b, v1.8h, v2.8h
142 0x20,0x60,0x62,0x6e = rsubhn2 v0.8h, v1.4s, v2.4s
143 0x20,0x60,0xa2,0x6e = rsubhn2 v0.4s, v1.2d, v2.2d
|
| /external/v8/src/arm64/ |
| macro-assembler-arm64.h | 425 V(rsubhn2, Rsubhn2) \
[all...] |
| assembler-arm64.h | [all...] |
| simulator-arm64.h | [all...] |
| assembler-arm64.cc | [all...] |
| simulator-arm64.cc | [all...] |
| simulator-logic-arm64.cc | 2818 LogicVRegister Simulator::rsubhn2(VectorFormat vform, LogicVRegister dst, function in class:v8::internal::Simulator
[all...] |
| /external/vixl/test/aarch64/ |
| test-trace-aarch64.cc | [all...] |
| test-cpu-features-aarch64.cc | [all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | [all...] |
| macro-assembler-aarch64.h | [all...] |
| simulator-aarch64.h | [all...] |
| logic-aarch64.cc | 3552 LogicVRegister Simulator::rsubhn2(VectorFormat vform, function in class:vixl::aarch64::Simulator
[all...] |
| simulator-aarch64.cc | [all...] |
| assembler-aarch64.cc | [all...] |
