| /external/u-boot/drivers/ddr/marvell/axp/ |
| ddr3_hw_training.c | 700 u32 *sdram_offset = (u32 *)RESUME_TRAINING_VALUES_ADDR; local
744 (*sdram_offset) = val;
745 crc += *sdram_offset;
746 sdram_offset++;
755 *sdram_offset = val;
756 crc += *sdram_offset;
757 sdram_offset++;
764 *sdram_offset = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR);
765 crc += *sdram_offset;
766 sdram_offset++
793 u32 *sdram_offset = (u32 *)RESUME_TRAINING_VALUES_ADDR; local
872 u32 *sdram_offset = (u32 *)BOOT_INFO_ADDR; local
[all...] |
| ddr3_sdram.c | 155 * sdram_offset offset address to the SDRAM
165 u32 pattern_len, u32 sdram_offset, int write,
184 ddr3_dram_sram_burst((u32)pattern, sdram_offset, pattern_len);
186 ddr3_dram_sram_burst(sdram_offset, (u32)sdram_data, pattern_len);
211 * sdram_offset offset address to the SDRAM
221 u32 sdram_offset)
293 u32 sdram_offset, pup_groups, tmp_pup; local
318 sdram_offset = SDRAM_PBS_I_OFFS + pbs_pattern_idx * SDRAM_PBS_NEXT_OFFS;
329 ddr3_dram_sram_burst((u32)pattern_ptr, sdram_offset,
333 ddr3_dram_sram_read(sdram_offset, (u32)sdram_data, LEN_PBS_PATTERN)
[all...] |
| ddr3_hw_training.h | 336 u32 pattern_len, u32 sdram_offset, int write,
341 u32 sdram_offset, int write, int mask,
346 u32 pattern_len, u32 sdram_offset, int write,
351 u32 sdram_offset);
|
| ddr3_dqs.c | 309 u32 sdram_offset; local
337 sdram_offset = cs_count * (SDRAM_CS_SIZE + 1);
338 sdram_offset += ((is_tx == 1) ?
416 sdram_offset +
961 u32 sdram_offset; local
979 sdram_offset = cs * SDRAM_CS_SIZE + SDRAM_DQS_RX_OFFS +
1007 sdram_offset, 0,
1122 u32 sdram_offset; local
1135 sdram_offset = cs * SDRAM_CS_SIZE + SDRAM_DQS_RX_OFFS;
[all...] |
| ddr3_read_leveling.c | 404 repeat_max_cnt, sdram_offset, locked_sum; local
456 sdram_offset = cs * (SDRAM_CS_SIZE + 1) + SDRAM_RL_OFFS;
461 sdram_offset, 0, 0, NULL, 0))
756 repeat_max_cnt, sdram_offset, final_sum, locked_sum; local
810 sdram_offset = cs * (SDRAM_CS_SIZE + 1) + SDRAM_RL_OFFS;
815 sdram_offset, 0, 0, NULL, 0))
[all...] |
| ddr3_write_leveling.c | 186 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; local
263 sdram_offset =
268 sdram_offset,
274 ddr3_dram_sram_burst(sdram_offset,
[all...] |
