| /external/capstone/bindings/java/capstone/ |
| X86.java | 79 public int sib_base; field in class:X86.UnionOpInfo
98 "modrm", "sib", "disp", "sib_index", "sib_scale", "sib_base", "sse_cc", "avx_cc", "avx_sae", "avx_rm", "op_count", "op");
133 sibBase = e.sib_base;
|
| /external/capstone/bindings/ocaml/ |
| x86.ml | 39 sib_base: int; Record field in type:cs_x86
|
| test_x86.ml | 75 printf "\tsib_index: %s, sib_scale: %u, sib_base: %s\n"
78 (cs_reg_name handle x86.sib_base);
|
| ocaml.c | 354 Store_field(op_info_val, 9, Val_int(insn[j-1].detail->x86.sib_base));
|
| /external/capstone/cstool/ |
| cstool_x86.c | 35 if (x86->sib_base != X86_REG_INVALID)
36 printf("\t\tsib_base: %s\n", cs_reg_name(ud, x86->sib_base));
|
| /external/jemalloc_new/include/jemalloc/internal/ |
| bitmap.h | 268 size_t sib_base = bit + (ZU(1) << lg_bits_per_group); local
269 assert(sib_base > min_bit);
270 assert(sib_base > bit);
271 if (sib_base >= binfo->nbits) {
274 return bitmap_ffu(bitmap, binfo, sib_base);
|
| /external/capstone/bindings/python/ |
| test_x86.py | 59 if insn.sib_base != 0:
60 print("\t\tsib_base: %s" % (insn.reg_name(insn.sib_base)))
|
| /external/capstone/bindings/python/capstone/ |
| x86.py | 62 ('sib_base', ctypes.c_uint),
74 a.sib_base, a.sse_cc, a.avx_cc, a.avx_sae, a.avx_rm, \
|
| __init__.py | 553 self.sib_index, self.sib_scale, self.sib_base, self.sse_cc, \
|
| /external/capstone/tests/ |
| test_x86.c | 58 if (x86->sib_base != X86_REG_INVALID)
59 printf("\t\tsib_base: %s\n", cs_reg_name(handle, x86->sib_base));
|
| /external/capstone/arch/X86/ |
| X86Disassembler.c | 763 pub->detail->x86.sib_base = x86_map_sib_base(inter->sibBase);
|
| /external/capstone/bindings/python/pyx/ |
| ccapstone.pyx | 34 self.sib_index, self.sib_scale, self.sib_base, \
|
| /external/capstone/include/ |
| x86.h | 243 x86_reg sib_base; member in struct:cs_x86
[all...] |
| /external/capstone/bindings/vb6/ |
| mx86.bas | 403 sib_base As x86_reg ' SIB base register, or X86_REG_INVALID when irrelevant.
[all...] |
