| /device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/ |
| tegra_fiq_glue.c | 52 * Save elr_el3 and spsr_el3 from the saved context, and overwrite
56 fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3));
126 * We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so
130 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3));
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/include/ |
| tegra_private.h | 38 uint64_t spsr_el3; member in struct:pcpu_fiq_state
|
| /device/linaro/bootloader/arm-trusted-firmware/bl1/aarch64/ |
| bl1_exceptions.S | 183 msr spsr_el3, x1
253 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there
257 mrs x16, spsr_el3
|
| /device/linaro/bootloader/arm-trusted-firmware/bl31/aarch64/ |
| runtime_exceptions.S | 70 mrs x0, spsr_el3
349 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world
353 mrs x16, spsr_el3
|
| crash_reporting.S | 38 "daif", "mair_el3", "spsr_el3", "elr_el3", "ttbr0_el3",\
269 mrs x14, spsr_el3
|
| /external/u-boot/arch/arm/include/asm/ |
| macro.h | 202 msr spsr_el3, \tmp
221 msr spsr_el3, \tmp
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmExceptionLib/AArch64/ |
| ExceptionSupport.S | 149 mrs x3, spsr_el3 // Saved Processor Status Register 32bit
359 msr spsr_el3, x30 // Saved Processor Status Register 32bit
|
| /device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch64/ |
| arch_helpers.h | 186 DEFINE_SYSREG_RW_FUNCS(spsr_el3)
|
| /device/linaro/bootloader/arm-trusted-firmware/lib/el3_runtime/aarch64/ |
| context.S | 407 * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
413 msr spsr_el3, x16
|
| /external/capstone/suite/MC/AArch64/ |
| basic-a64-instructions.s.cs | [all...] |
