| /external/u-boot/arch/arm/mach-omap2/omap5/ |
| emif.c | 31 .tRRD = 10,
60 .tRRD = 2,
|
| sdram.c | 619 .tRRD = 10,
641 .tRRD = 2,
|
| /external/u-boot/arch/arm/mach-omap2/omap4/ |
| emif.c | 30 .tRRD = 10,
54 .tRRD = 10,
83 .tRRD = 2,
|
| sdram_elpida.c | 197 .tRRD = 10,
220 .tRRD = 10,
243 .tRRD = 10,
265 .tRRD = 2,
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| mrc.h | 86 uint32_t tRRD; // ACT to ACT command period (JESD79 specific to page size 1K/2K)
|
| gen5_iosf_sb_definitions.h | 112 uint32_t tRRD :2; /**<Row activation to Row activation Delay */
|
| meminit.c | 394 uint8_t TRP, TRCD, TRAS, TWR, TWTR, TRRD, TRTP, TFAW;
422 TRRD = MCEIL(mrc_params->params.tRRD, TCK);
437 Dtr1.field.tRRD = TRRD - 4; //4 bit DRAM Clock
[all...] |
| /external/u-boot/arch/arm/mach-sunxi/ |
| dram_sun9i.c | 130 struct dram_sun9i_timing tRRD;
390 const u32 tRRD = MAX(para->tRRD.ck, PS2CYCLES_ROUNDUP(para->tRRD.ps));
549 (MCTL_DIV2(tRRD) << 8) | (MCTL_DIV2(tRP) << 0),
641 writel((tRC << 26) | (tRRD << 22) | (tRAS << 16) |
900 .tRRD = { .ck = 4, .ps = 7500 },
|
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/ |
| MrcWrapper.h | 121 UINT32 tRRD; ///< ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds.
|
| MrcWrapper.c | 136 MrcData->params.tRRD = ItemData->tRRD;
152 DEBUG ((EFI_D_INFO, "MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n",
157 MrcData->params.tRRD,
[all...] |
| /external/u-boot/arch/arm/include/asm/ |
| emif.h | [all...] |
| /external/u-boot/arch/arm/mach-omap2/ |
| emif-common.c | 694 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
[all...] |
