| /external/u-boot/board/overo/ |
| spl.c | 22 * so we have to setup the DDR timings ourself on both banks.
24 void get_board_mem_timings(struct board_sdrc_timings *timings)
26 timings->mr = MICRON_V_MR_165;
29 timings->mcfg = MICRON_V_MCFG_165(256 << 20);
30 timings->ctrla = MICRON_V_ACTIMA_165;
31 timings->ctrlb = MICRON_V_ACTIMB_165;
32 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
36 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
37 timings->ctrla = MICRON_V_ACTIMA_200;
38 timings->ctrlb = MICRON_V_ACTIMB_200
[all...] |
| /external/u-boot/board/isee/igep00x0/ |
| spl.c | 13 * so we have to setup the DDR timings ourself on both banks.
15 void get_board_mem_timings(struct board_sdrc_timings *timings)
19 timings->mr = MICRON_V_MR_165;
23 timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
24 timings->ctrla = HYNIX_V_ACTIMA_200;
25 timings->ctrlb = HYNIX_V_ACTIMB_200;
28 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
29 timings->ctrla = MICRON_V_ACTIMA_200;
30 timings->ctrlb = MICRON_V_ACTIMB_200;
36 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz
[all...] |
| /external/u-boot/arch/arm/mach-imx/ |
| ddrmc-vf610.c | 107 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
117 writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
118 writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]);
120 writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]);
121 writel(DDRMC_CR12_WRLAT(timings->wrlat) |
122 DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
123 writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
124 DDRMC_CR13_TCCD(timings->tccd) |
125 DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval)
[all...] |
| /cts/tests/tests/util/src/android/util/cts/ |
| TimingLoggerTest.java | 35 TimingLogger timings = new TimingLogger(LOG_TAG, "testTimingLogger"); local
39 timings.reset(LOG_TAG, "testReset");
41 timings.reset();
45 timings.addSplit("first sleep");
48 timings.addSplit("second sleep");
51 timings.addSplit("third sleep");
53 timings.dumpToLog();
|
| /external/u-boot/board/quipos/cairo/ |
| cairo.c | 63 * so we have to setup the DDR timings ourself on the first bank. This
69 void get_board_mem_timings(struct board_sdrc_timings *timings)
71 timings->sharing = SAMSUNG_SHARING;
72 timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20);
73 timings->ctrla = SAMSUNG_V_ACTIMA_165;
74 timings->ctrlb = SAMSUNG_V_ACTIMB_165;
75 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
76 timings->mr = SAMSUNG_V_MR_165;
|
| /art/runtime/base/ |
| timing_logger_test.cc | 32 const auto& timings = logger.GetTimings(); local
33 EXPECT_EQ(2U, timings.size()); // Start, End splits
34 EXPECT_TRUE(timings[0].IsStartTiming());
35 EXPECT_STREQ(timings[0].GetName(), split1name);
36 EXPECT_TRUE(timings[1].IsEndTiming());
49 // Get the timings and verify that they are sane.
50 const auto& timings = logger.GetTimings(); local
51 // 6 timings in the timing logger at this point.
52 EXPECT_EQ(6U, timings.size());
53 EXPECT_TRUE(timings[0].IsStartTiming())
79 const auto& timings = logger.GetTimings(); local
124 const auto& timings = logger.GetTimings(); local
154 const auto& timings = logger.GetTimings(); local
[all...] |
| /external/u-boot/arch/arm/mach-omap2/omap3/ |
| sdrc.c | 98 * - Takes CS and associated timings and initalize SDRAM
102 struct board_sdrc_timings *timings)
104 /* Setup timings we got from the board. */
105 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
106 writel(timings->ctrla, &sdrc_actim_base->ctrla);
107 writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
108 writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
113 writel(timings->mr, &sdrc_base->cs[cs].mr);
132 struct board_sdrc_timings timings; local
137 /* set some default timings */
[all...] |
| /external/u-boot/board/corscience/tricorder/ |
| tricorder.c | 159 * so we have to setup the DDR timings ourself on the first bank. This
163 void get_board_mem_timings(struct board_sdrc_timings *timings)
170 /* use optimized timings for our SDRAM device */
171 timings->mcfg = MCFG((256 << 20), 14);
181 timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC,
191 timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE,
194 timings->mr = MICRON_V_MR_165;
195 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
197 /* use conservative beagleboard timings as default */
198 timings->mcfg = MICRON_V_MCFG_165(128 << 20)
[all...] |
| /external/u-boot/board/ti/beagle/ |
| beagle.c | 155 * so we have to setup the DDR timings ourself on both banks.
157 void get_board_mem_timings(struct board_sdrc_timings *timings)
163 * we know what timings to use. If we can't identify it then
168 timings->mr = MICRON_V_MR_165;
173 timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
174 timings->ctrla = NUMONYX_V_ACTIMA_165;
175 timings->ctrlb = NUMONYX_V_ACTIMB_165;
176 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
180 timings->mcfg = MICRON_V_MCFG_165(128 << 20);
181 timings->ctrla = MICRON_V_ACTIMA_165
[all...] |
| /external/u-boot/board/technexion/tao3530/ |
| tao3530.c | 73 * so we have to setup the DDR timings ourself on both banks.
75 void get_board_mem_timings(struct board_sdrc_timings *timings)
91 timings->mcfg = MCFG(256 << 20, 14); /* RAS-width 14 */
92 timings->ctrla = HYNIX_V_ACTIMA_165;
93 timings->ctrlb = HYNIX_V_ACTIMB_165;
96 timings->mcfg = MCFG(128 << 20, 13); /* RAS-width 13 */
97 timings->ctrla = MICRON_V_ACTIMA_165;
98 timings->ctrlb = MICRON_V_ACTIMB_165;
101 timings->mr = MICRON_V_MR_165;
102 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz
[all...] |
| /external/u-boot/board/lg/sniper/ |
| sniper.c | 67 void get_board_mem_timings(struct board_sdrc_timings *timings)
69 timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
70 timings->ctrla = HYNIX_V_ACTIMA_200;
71 timings->ctrlb = HYNIX_V_ACTIMB_200;
72 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
73 timings->mr = MICRON_V_MR_165;
|
| /external/u-boot/board/timll/devkit8000/ |
| devkit8000.c | 191 * so we have to setup the DDR timings ourself on the first bank. This
195 void get_board_mem_timings(struct board_sdrc_timings *timings)
198 timings->mcfg = MICRON_V_MCFG_165(128 << 20);
199 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
201 /* AC timings */
202 timings->ctrla = MICRON_V_ACTIMA_165;
203 timings->ctrlb = MICRON_V_ACTIMB_165;
205 timings->mr = MICRON_V_MR_165;
|
| /external/u-boot/drivers/mtd/nand/ |
| nand_timings.c | 19 .timings.sdr = {
61 .timings.sdr = {
103 .timings.sdr = {
145 .timings.sdr = {
187 .timings.sdr = {
229 .timings.sdr = {
272 * timings according to the given ONFI timing mode
280 return &onfi_sdr_timings[mode].timings.sdr;
304 * Initialize timings that cannot be deduced from timing mode:
310 struct nand_sdr_timings *timings = &iface->timings.sdr local
[all...] |
| sunxi_nand.c | 1349 const struct nand_sdr_timings *timings; local
1601 const struct nand_sdr_timings *timings; local
[all...] |
| /art/dex2oat/driver/ |
| compiler_driver.h | 106 TimingLogger* timings,
112 TimingLogger* timings)
230 void LoadImageClasses(TimingLogger* timings, /*inout*/ HashSet<std::string>* image_classes)
238 TimingLogger* timings)
245 TimingLogger* timings)
252 TimingLogger* timings,
257 TimingLogger* timings,
265 TimingLogger* timings)
270 TimingLogger* timings);
276 TimingLogger* timings)
[all...] |
| /art/dex2oat/ |
| common_compiler_driver_test.cc | 35 TimingLogger* timings) {
36 TimingLogger::ScopedTiming t(__FUNCTION__, timings);
43 timings,
51 compiler_driver_->CompileAll(class_loader, dex_files, timings);
|
| common_compiler_driver_test.h | 42 TimingLogger* timings) REQUIRES(!Locks::mutator_lock_);
|
| /external/u-boot/board/ti/evm/ |
| evm.c | 139 * so we have to setup the DDR timings ourself on the first bank. This
143 void get_board_mem_timings(struct board_sdrc_timings *timings)
149 * we know what timings to use. To map the ID values please see
156 timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
157 timings->ctrla = HYNIX_V_ACTIMA_200;
158 timings->ctrlb = HYNIX_V_ACTIMB_200;
161 timings->mcfg = MICRON_V_MCFG_165(128 << 20);
162 timings->ctrla = MICRON_V_ACTIMA_165;
163 timings->ctrlb = MICRON_V_ACTIMB_165;
165 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz
[all...] |
| /device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.2/Lib/ |
| profile.py | 144 self.timings[]. The index is always the name stored in self.cur[-3].
162 self.timings = {}
300 timings = self.timings
301 if fn in timings:
302 cc, ns, tt, ct, callers = timings[fn]
303 timings[fn] = cc, ns + 1, tt, ct, callers
305 timings[fn] = 0, 0, 0, 0, {}
311 timings = self.timings
[all...] |
| /external/python/cpython2/Lib/ |
| profile.py | 135 self.timings[]. The index is always the name stored in self.cur[-3].
153 self.timings = {}
291 timings = self.timings
292 if fn in timings:
293 cc, ns, tt, ct, callers = timings[fn]
294 timings[fn] = cc, ns + 1, tt, ct, callers
296 timings[fn] = 0, 0, 0, 0, {}
302 timings = self.timings
[all...] |
| /external/python/cpython3/Lib/ |
| profile.py | 126 self.timings[]. The index is always the name stored in self.cur[-3].
144 self.timings = {}
270 timings = self.timings
271 if fn in timings:
272 cc, ns, tt, ct, callers = timings[fn]
273 timings[fn] = cc, ns + 1, tt, ct, callers
275 timings[fn] = 0, 0, 0, 0, {}
281 timings = self.timings
[all...] |
| /cts/tests/tests/os/src/android/os/cts/ |
| VibratorTest.java | 112 final long[] timings = new long[] {100, 200, 300, 400, 500}; local
114 VibrationEffect waveform = VibrationEffect.createWaveform(timings, amplitudes, -1);
118 waveform = VibrationEffect.createWaveform(timings, amplitudes, 0);
|
| /art/dex2oat/dex/ |
| dex_to_dex_decompiler_test.cc | 41 TimingLogger timings("DexToDexDecompilerTest::CompileAll", false, false);
49 CommonCompilerDriverTest::CompileAll(class_loader, dex_files, &timings);
|
| /external/u-boot/arch/arm/dts/ |
| am335x-pxm50.dts | 41 display-timings {
|
| /external/u-boot/board/logicpd/omap3som/ |
| omap3logic.c | 88 * so we have to setup the DDR timings ourself on the first bank. This
92 void get_board_mem_timings(struct board_sdrc_timings *timings)
94 timings->mr = MICRON_V_MR_165;
96 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
97 timings->ctrla = MICRON_V_ACTIMA_200;
98 timings->ctrlb = MICRON_V_ACTIMB_200;
99 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
|
