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Searched
refs:training_result
(Results
1 - 8
of
8
) sorted by null
/external/u-boot/drivers/ddr/marvell/a38x/
ddr3_debug.c
188
memcpy(result,
training_result
,
201
return
training_result
[stage];
401
(
training_result
[INIT_CONTROLLER]
408
(
training_result
[SET_LOW_FREQ]
415
(
training_result
[LOAD_PATTERN]
422
(
training_result
[SET_MEDIUM_FREQ]
429
(
training_result
[WRITE_LEVELING]
436
(
training_result
[LOAD_PATTERN_2]
443
(
training_result
[READ_LEVELING]
450
(
training_result
[WRITE_LEVELING_SUPP
[
all
...]
ddr3_training_leveling.c
85
training_result
[training_stage][if_id] = TEST_SUCCESS;
256
training_result
[training_stage][if_id] =
330
if (
training_result
[training_stage][if_id] == TEST_FAILED)
460
training_result
[training_stage][if_id] = TEST_SUCCESS;
738
training_result
[training_stage][if_id] = TEST_FAILED;
783
if (
training_result
[training_stage][if_id] == TEST_FAILED)
852
training_result
[training_stage][if_id] = TEST_SUCCESS;
[
all
...]
ddr3_training_centralization.c
54
enum hws_training_ip_stat
training_result
[MAX_INTERFACE_NUM];
local
129
PARAM_NOT_CARE,
training_result
);
495
enum hws_training_ip_stat
training_result
[MAX_INTERFACE_NUM];
local
542
PARAM_NOT_CARE,
training_result
);
ddr3_init.h
95
extern enum hws_result
training_result
[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
ddr3_training_bist.c
226
enum hws_training_ip_stat
training_result
;
local
233
TIP_ITERATION_NUM, pattern, EDGE_FP, CS_SINGLE, cs, &
training_result
);
ddr3_training_pbs.c
715
training_result
[training_stage][if_id]
722
training_result
[
724
(
training_result
[training_stage]
ddr3_training.c
37
enum hws_result
training_result
[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
variable in typeref:enum:hws_result
[
all
...]
ddr3_training_ip_engine.c
[
all
...]
Completed in 243 milliseconds