| /external/llvm/test/MC/AMDGPU/ |
| vopc.s | 25 v_cmp_lt_f32 vcc, v255, v255
26 // SICI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x03,0x7c]
27 // VI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x83,0x7c]
|
| vop_sdwa.s | 33 // VI: v_min_u32_sdwa v255, v4, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:WORD_1 ; encoding: [0xf9,0x02,0xfe,0x1d,0x04,0x04,0x02,0x05]
34 v_min_u32 v255, v4, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:WORD_1
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
| vop1-gfx9.s | 31 v_sat_pk_u8_i16 v255, v1
32 // GFX9: v_sat_pk_u8_i16_e32 v255, v1 ; encoding: [0x01,0x9f,0xfe,0x7f]
43 v_screen_partition_4se_b32 v5, v255
44 // GFX9: v_screen_partition_4se_b32_e32 v5, v255 ; encoding: [0xff,0x6f,0x0a,0x7e]
|
| vopc.s | 25 v_cmp_lt_f32 vcc, v255, v255
26 // SICI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x03,0x7c]
27 // VI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x83,0x7c]
|
| mimg-err.s | 44 image_atomic_add v[6:7], v255, s[8:15] dmask:0x2
47 image_atomic_add v[6:7], v255, s[8:15] dmask:0xf
56 image_atomic_add v[6:7], v255, s[8:15] dmask:0x2 tfe
|
| gfx9_asm_all.s | 7 ds_add_u32 v255, v2 offset:65535
10 ds_add_u32 v1, v255 offset:65535
28 ds_sub_u32 v255, v2 offset:65535
31 ds_sub_u32 v1, v255 offset:65535
49 ds_rsub_u32 v255, v2 offset:65535
52 ds_rsub_u32 v1, v255 offset:65535
70 ds_inc_u32 v255, v2 offset:65535
73 ds_inc_u32 v1, v255 offset:65535
91 ds_dec_u32 v255, v2 offset:65535
94 ds_dec_u32 v1, v255 offset:6553
[all...] |
| mubuf-gfx9.s | 60 buffer_store_format_d16_hi_x v255, off, s[12:15], s4
61 // GFX9: buffer_store_format_d16_hi_x v255, off, s[12:15], s4 ; encoding: [0x00,0x00,0x9c,0xe0,0x00,0xff,0x03,0x04]
64 buffer_store_format_d16_hi_x v255, off, s[12:15], s4 offset:4095
65 // GFX9: buffer_store_format_d16_hi_x v255, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x9c,0xe0,0x00,0xff,0x03,0x04]
|
| vop3-errs.s | 65 v_interp_p2_f32_e64 v255, v2, attr0.x high
68 v_interp_p2_f32_e64 v255, v2, attr0.x v0
|
| gfx8_asm_all.s | 6 ds_add_u32 v255, v2 offset:65535
9 ds_add_u32 v1, v255 offset:65535
27 ds_sub_u32 v255, v2 offset:65535
30 ds_sub_u32 v1, v255 offset:65535
48 ds_rsub_u32 v255, v2 offset:65535
51 ds_rsub_u32 v1, v255 offset:65535
69 ds_inc_u32 v255, v2 offset:65535
72 ds_inc_u32 v1, v255 offset:65535
90 ds_dec_u32 v255, v2 offset:65535
93 ds_dec_u32 v1, v255 offset:6553
[all...] |
| gfx7_asm_all.s | 6 ds_add_u32 v255, v2 offset:65535
9 ds_add_u32 v1, v255 offset:65535
27 ds_sub_u32 v255, v2 offset:65535
30 ds_sub_u32 v1, v255 offset:65535
48 ds_rsub_u32 v255, v2 offset:65535
51 ds_rsub_u32 v1, v255 offset:65535
69 ds_inc_u32 v255, v2 offset:65535
72 ds_inc_u32 v1, v255 offset:65535
90 ds_dec_u32 v255, v2 offset:65535
93 ds_dec_u32 v1, v255 offset:6553
[all...] |
| vop3p-err.s | 79 v_pk_add_f16 v255, s1, s2
|
| dl-insts.s | 10 v_fmac_f32 v255, v1, v2
12 v_fmac_f32 v5, v255, v2
44 v_fmac_f32 v5, v1, v255
49 v_fmac_f32_e64 v255, v1, v2
51 v_fmac_f32_e64 v5, v255, v2
79 v_fmac_f32_e64 v5, v1, v255
130 v_fmac_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
132 v_fmac_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
134 v_fmac_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
195 v_xnor_b32 v255, v1, v
[all...] |
| ds.s | 18 ds_add_src2_f32 v255 offset:65535
20 // VI: ds_add_src2_f32 v255 offset:65535 ; encoding: [0xff,0xff,0x2a,0xd9,0xff,0x00,0x00,0x00]
258 ds_wrxchg2st64_rtn_b32 v[0:1], v0, v255, v0 offset0:127 offset1:255
259 // SICI: ds_wrxchg2st64_rtn_b32 v[0:1], v0, v255, v0 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0xbc,0xd8,0x00,0xff,0x00,0x00]
260 // VI: ds_wrxchg2st64_rtn_b32 v[0:1], v0, v255, v0 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0x5e,0xd8,0x00,0xff,0x00,0x00]
467 ds_wrxchg2st64_rtn_b64 v[0:3], v255, v[0:1], v[0:1] offset0:127 offset1:255
468 // SICI: ds_wrxchg2st64_rtn_b64 v[0:3], v255, v[0:1], v[0:1] offset0:127 offset1:255 ; encoding: [0x7f,0xff,0xbc,0xd9,0xff,0x00,0x00,0x00]
469 // VI: ds_wrxchg2st64_rtn_b64 v[0:3], v255, v[0:1], v[0:1] offset0:127 offset1:255 ; encoding: [0x7f,0xff,0xde,0xd8,0xff,0x00,0x00,0x00]
[all...] |
| dl-insts-err.s | 383 v_dot2_f32_f16 v255, s1, s2, s3
385 v_dot2_i32_i16 v255, s1, s2, s3
387 v_dot2_u32_u16 v255, s1, s2, s3
|
| vop3.s | 415 v_cmpx_class_f16_e64 s[10:11], v255, s2
417 // VI: v_cmpx_class_f16_e64 s[10:11], v255, s2 ; encoding: [0x0a,0x00,0x15,0xd0,0xff,0x05,0x00,0x00]
647 v_interp_p2_f32_e64 v255, v2, attr0.x
649 // VI: v_interp_p2_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
[all...] |
| vop2.s | 127 // SICI: v_writelane_b32 v255, 0xaf123456, 2 ; encoding: [0xff,0x04,0xff,0x05,0x56,0x34,0x12,0xaf]
129 v_writelane_b32 v255, 0xaf123456, 2
|
| mimg.s | 294 image_atomic_add v[6:7], v255, s[8:15] dmask:0x3
295 // SICI: image_atomic_add v[6:7], v255, s[8:15] dmask:0x3 ; encoding: [0x00,0x03,0x44,0xf0,0xff,0x06,0x02,0x00]
296 // GFX89: image_atomic_add v[6:7], v255, s[8:15] dmask:0x3 ; encoding: [0x00,0x03,0x48,0xf0,0xff,0x06,0x02,0x00]
|
| vop3-gfx9.s | 445 v_sat_pk_u8_i16_e64 v5, v255
446 // GFX9: v_sat_pk_u8_i16_e64 v5, v255 ; encoding: [0x05,0x00,0x8f,0xd1,0xff,0x01,0x00,0x00]
|
| vop_sdwa.s | 31 // GFX89: v_min_u32_sdwa v255, v4, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:WORD_1 ; encoding: [0xf9,0x02,0xfe,0x1d,0x04,0x04,0x02,0x05]
32 v_min_u32 v255, v4, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:WORD_1
[all...] |
| /external/webp/src/dsp/ |
| upsampling_neon.c | 82 #define v255 vdup_n_u8(255) macro
98 INIT_VECTOR4(r_g_b_v255, r, g, b, v255); \
104 INIT_VECTOR4(b_g_r_v255, b, g, r, v255); \
110 INIT_VECTOR4(v255_r_g_b, v255, r, g, b); \
122 const uint8x8_t ba = vsri_n_u8(b, v255, 4); /* shift a, insert b */ \
|
