| /external/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| fd5_zsa.c | 65 if (!(cso->stencil->enabled || cso->alpha.enabled || !cso->depth.writemask))
76 if (cso->depth.writemask)
90 A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |
103 A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(bs->writemask) |
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| /external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| fd2_zsa.c | 55 if (cso->depth.writemask)
69 A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |
83 A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(bs->writemask) |
|
| /external/mesa3d/src/gallium/drivers/freedreno/a3xx/ |
| fd3_zsa.c | 58 if (cso->depth.writemask)
73 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |
87 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(bs->writemask) |
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_rename_regs.c | 72 unsigned writemask; local
86 writemask = rc_variable_writemask_sum(var);
87 rc_variable_change_dst(var, new_index, writemask);
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| radeon_pair_regalloc.c | 59 unsigned int Writemask;
289 unsigned int writemask,
299 if (classes[i].Writemasks[j] == writemask) {
332 unsigned int writemask = rc_variable_writemask_sum(variable); local
344 writemask = RC_MASK_XYZW;
350 class_index = find_class(classes, writemask, 3);
365 writemask, c.Writemasks[i]);
372 * then the writemask will be set to RC_MASK_XYZW
435 class_index = find_class(classes, writemask,
444 variable->Dst.Index, writemask);
560 unsigned int chan, writemask = 0; local
628 unsigned int writemask = reg_get_writemask(reg); local
[all...] |
| radeon_variable.c | 39 * Rewrite the index and writemask for the destination register of var
61 if (var_ptr->Dst.WriteMask == RC_MASK_W) {
157 unsigned int mask = var->Readers[i].WriteMask;
286 new->Dst.WriteMask = DstWriteMask;
321 unsigned int writemask; local
333 if (sub_inst->WriteMask) {
335 writemask = sub_inst->WriteMask;
338 writemask = sub_inst->OutputWriteMask;
340 writemask = 0
393 unsigned int writemask = 0; local
[all...] |
| radeon_opcodes.h | 285 unsigned int writemask,
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| /external/mesa3d/src/intel/compiler/ |
| brw_vec4_cmod_propagation.cpp | 75 (scan_inst->dst.writemask != WRITEMASK_X &&
76 scan_inst->dst.writemask != WRITEMASK_XYZW) ||
77 (scan_inst->dst.writemask == WRITEMASK_XYZW &&
79 (inst->dst.writemask & ~scan_inst->dst.writemask) != 0 ||
|
| test_vec4_register_coalesce.cpp | 134 m0.writemask = WRITEMASK_X;
153 m0.writemask = WRITEMASK_X;
157 m1.writemask = WRITEMASK_XYZW;
179 m0.writemask = WRITEMASK_Y;
190 EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y);
203 to.writemask = WRITEMASK_Y;
216 EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y);
229 to.writemask = WRITEMASK_Y;
|
| brw_vec4_dead_code_eliminate.cpp | 85 if (!result_live[c] && inst->dst.writemask & (1 << c)) {
86 inst->dst.writemask &= ~(1 << c);
89 if (inst->dst.writemask == 0) {
116 if (inst->dst.writemask & (1 << c)) {
|
| brw_vec4_tcs.h | 68 void emit_urb_write(const src_reg &value, unsigned writemask,
|
| brw_vec4_surface_builder.cpp | 45 bld.MOV(writemask(offset(dst, 8, i * dst_stride / 4),
72 bld.MOV(writemask(tmp, mask), src);
74 bld.MOV(writemask(tmp, ~mask), brw_imm_d(0));
216 bld.MOV(writemask(srcs, WRITEMASK_X),
221 bld.MOV(writemask(srcs, WRITEMASK_Y),
251 ubld.MOV(writemask(dst, WRITEMASK_W), brw_imm_d(0x11));
324 bld.MOV(writemask(srcs, WRITEMASK_X), src0);
326 bld.MOV(writemask(srcs, WRITEMASK_Y), src1);
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| brw_vec4_visitor.cpp | 354 if (devinfo->gen == 6 && dst.writemask != WRITEMASK_XYZW) {
427 tmp_dst.writemask = WRITEMASK_XY;
472 tmp_dst.writemask = WRITEMASK_X;
475 tmp_dst.writemask = WRITEMASK_Y;
478 dst.writemask = WRITEMASK_XY;
717 this->writemask = WRITEMASK_XYZW;
719 this->writemask = (1 << type->vector_elements) - 1;
751 y_times_a.writemask = dst.writemask;
752 one_minus_a.writemask = dst.writemask
979 int writemask = devinfo->gen == 4 ? WRITEMASK_W : WRITEMASK_X; local
1008 int mrf, writemask; local
[all...] |
| brw_vec4.cpp | 80 this->swizzle = brw_swizzle_for_mask(reg.writemask);
89 this->writemask = WRITEMASK_XYZW;
106 unsigned writemask)
113 this->writemask = writemask;
117 unsigned writemask)
124 this->writemask = writemask;
137 this->writemask = brw_mask_for_swizzle(reg.swizzle);
390 unsigned writemask = 0 local
[all...] |
| brw_vec4_gs_nir.cpp | 60 /* Write to dst reg taking into account original writemask */
62 dest.writemask = brw_writemask_for_size(instr->num_components);
74 dest.writemask = brw_writemask_for_size(instr->num_components);
|
| /external/mesa3d/src/mesa/state_tracker/ |
| st_glsl_to_tgsi_private.cpp | 187 this->writemask = WRITEMASK_XYZW;
195 st_dst_reg::st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type, int index)
201 this->writemask = writemask;
209 st_dst_reg::st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type)
215 this->writemask = writemask;
229 this->writemask = 0;
246 this->writemask = reg.writemask;
[all...] |
| st_glsl_to_tgsi_private.h | 89 st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type, int index);
91 st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type);
102 unsigned writemask:4; /**< Bitfield of WRITEMASK_[XYZW] */
|
| st_atom_depth.c | 111 dsa->depth.writemask = ctx->Depth.Mask;
128 dsa->stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff;
139 dsa->stencil[1].writemask = ctx->Stencil.WriteMask[back] & 0xff;
|
| /external/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
| fd4_zsa.c | 58 if (cso->depth.writemask)
75 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |
89 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(bs->writemask) |
|
| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| etnaviv_zsa.c | 52 !so->depth.writemask;
62 if(so->stencil[i].writemask == 0)
99 COND(so->depth.writemask, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE) |
119 VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(so->stencil[0].writemask);
|
| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_blit.h | 64 uint writemask);
|
| u_blit.c | 162 set_fragment_shader(struct blit_state *ctx, uint writemask,
180 if (!ctx->fs[pipe_tex][writemask][idx]) {
185 ctx->fs[pipe_tex][writemask][idx] =
188 writemask,
192 cso_set_fragment_shader_handle(ctx->cso, ctx->fs[pipe_tex][writemask][idx]);
360 * \param writemask bitmask of PIPE_MASK_[RGBAZS]. Controls which channels
375 uint writemask)
406 blit_depth = is_depth && (writemask & PIPE_MASK_Z);
407 blit_stencil = is_stencil && (writemask & PIPE_MASK_S);
410 assert((writemask & PIPE_MASK_RGBA) == 0)
[all...] |
| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_pipe_depthstencil.c | 151 /* SVGA3D has one ref/mask/writemask triple shared between front &
155 ds->stencil_writemask = templ->stencil[0].writemask & 0xff;
174 ds->stencil_writemask = templ->stencil[1].writemask & 0xff;
183 if (templ->stencil[1].writemask != templ->stencil[0].writemask) {
185 "two-sided stencil writemask not supported "
187 templ->stencil[0].writemask,
188 templ->stencil[1].writemask);
203 ds->zwriteenable = templ->depth.writemask;
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_scan.c | 945 arrays[dst->Indirect.ArrayID - 1].writemask |= dst->Register.WriteMask;
984 unsigned writemask = 0; local
1008 unsigned writemask = 0; local
1082 unsigned writemask = get_inst_tessfactor_writemask(info, inst); local
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/ |
| r300_hyperz.c | 175 assert(!dsa->dsa.depth.writemask);
190 /* If writemask is disabled, the HiZ memory will not be changed,
192 if (dsa->dsa.depth.writemask) {
224 return s->enabled && s->writemask &&
236 if (dsa->depth.enabled && dsa->depth.writemask &&
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