| /device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/include/ |
| hi6220_regs_pin.h | 18 #define IOMG_GPIO24 (IOMG_BASE + 0x140)
|
| /external/bouncycastle/bcprov/src/main/java/org/bouncycastle/math/ec/custom/sec/ |
| SecP192K1FieldElement.java | 171 int[] x140 = x35; local
172 SecP192K1Field.squareN(x70, 70, x140);
173 SecP192K1Field.multiply(x140, x70, x140);
175 SecP192K1Field.squareN(x140, 19, x159);
|
| /external/bouncycastle/repackaged/bcprov/src/main/java/com/android/org/bouncycastle/math/ec/custom/sec/ |
| SecP192K1FieldElement.java | 175 int[] x140 = x35; local
176 SecP192K1Field.squareN(x70, 70, x140);
177 SecP192K1Field.multiply(x140, x70, x140);
179 SecP192K1Field.squareN(x140, 19, x159);
|
| /device/linaro/bootloader/edk2/StdLib/Include/Ipf/machine/ |
| setjmp.h | 77 #define J_F26 0x140
|
| /external/u-boot/arch/arm/dts/ |
| am335x-draco.dts | 73 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.mii1_rxd0 */
85 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
| am335x-bone-common.dtsi | 124 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
143 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
| /external/u-boot/arch/arm/mach-uniphier/sbc/ |
| sbc-regs.h | 57 #define SBCTRL44 (SBCTRL_BASE + 0x140)
|
| /external/u-boot/drivers/pinctrl/exynos/ |
| pinctrl-exynos7420.c | 67 EXYNOS_PIN_BANK(6, 0x140, "gpd6"),
|
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/ |
| ia_64gen.h | 69 #define T_R22 0x140
145 #define J_F26 0x140
187 #define C_F23 0x140
|
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/Pei/PeiLib/Ipf/ |
| Ia_64Gen.h | 72 #define T_R22 0x140
148 #define J_F26 0x140
190 #define C_F23 0x140
|
| /device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/Ipf/ |
| Ia64gen.h | 63 #define T_R22 0x140
139 #define J_F26 0x140
181 #define C_F23 0x140
|
| /external/libunwind/src/ia64/ |
| offsets.h | 77 #define LINUX_OLD_PT_B0_OFF 0x140
|
| /external/u-boot/arch/arm/include/asm/arch-meson/ |
| clock.h | 35 #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
|
| /external/u-boot/arch/m68k/include/asm/ |
| m5249.h | 93 #define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/ |
| ddr_rk3368.h | 68 #define DDR_PCTL_TCKESR 0x140
176 #define DDR_PHY_REG50 0x140
|
| /external/libdrm/freedreno/ |
| freedreno_ringbuffer.c | 73 start = &ring->start[0x140];
|
| /external/libunwind/src/x86/ |
| offsets.h | 86 #define LINUX_FPSTATE_XMM3_OFF 0x140
|
| /external/u-boot/arch/arm/include/asm/arch-mx6/ |
| mx6sl_pins.h | 54 MX6_PAD_FEC_RXD1__FEC_RX_DATA1 = IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0),
|
| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| grf_rk3328.h | 49 u32 reserved2[(0x200 - 0x140) / 4];
|
| /external/u-boot/arch/arm/mach-at91/ |
| mpddrc.c | 14 #define SAMA5D3_MPDDRC_VERSION 0x140
|
| /external/u-boot/arch/arm/mach-socfpga/include/mach/ |
| clock_manager_arria10.h | 108 #define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
|
| /external/u-boot/drivers/clk/renesas/ |
| renesas-cpg-mssr.c | 48 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
|
| /external/u-boot/drivers/phy/marvell/ |
| comphy.h | 43 #define COMMON_SELECTOR_PHY_OFFSET 0x140
|
| /external/u-boot/include/net/pfe_eth/pfe/cbus/ |
| tmu_csr.h | 116 #define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140)
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmExceptionLib/AArch64/ |
| ExceptionSupport.S | 63 UINT64 V4[2]; 0x140
282 stp q20, q21, [x28, #0x140]
330 ldp q20, q21, [x28, #0x140]
|
