| /external/llvm/lib/ExecutionEngine/ |
| ExecutionEngine.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | 857 unsigned Dst = MI.getOperand(0).getReg();
858 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
859 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
868 .addReg(Dst, RegState::Implicit | RegState::Define);
871 .addReg(Dst, RegState::Implicit | RegState::Define);
876 .addReg(Dst, RegState::Implicit | RegState::Define);
879 .addReg(Dst, RegState::Implicit | RegState::Define);
886 unsigned Dst = MI.getOperand(0).getReg();
887 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
888 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1)
[all...] |
| R600ISelLowering.cpp | 223 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/MC/ |
| MCDwarf.cpp | 577 const MachineLocation &Dst = Instr.getDestination();
582 if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) {
605 assert(Dst.isReg() && "Machine move not supported yet.");
608 if (VerboseAsm) Streamer.AddComment(Twine("Reg ") + Twine(Dst.getReg()));
609 Streamer.EmitULEB128IntValue(Dst.getReg());
614 int Offset = Dst.getOffset();
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/ExecutionEngine/ |
| ExecutionEngine.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-c-test/ |
| echo.cpp | 158 static ValueMap clone_params(LLVMValueRef Src, LLVMValueRef Dst) {
160 if (Count != LLVMCountParams(Dst))
168 LLVMValueRef DstFirst = LLVMGetFirstParam(Dst);
170 LLVMValueRef DstLast = LLVMGetLastParam(Dst);
242 LLVMValueRef Dst = LLVMGetNamedFunction(M, Name);
243 if (Dst)
244 return Dst;
251 LLVMValueRef Dst = LLVMGetNamedGlobal(M, Name);
252 if (Dst)
253 return Dst;
[all...] |
| /device/linaro/bootloader/edk2/BaseTools/Source/C/TianoCompress/ |
| TianoCompress.c | [all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Include/Library/ |
| NetLib.h | 141 IP4_ADDR Dst;
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/SetupBrowserDxe/ |
| Setup.c | [all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| CStringChecker.cpp | [all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| ExprEngine.cpp | 443 ExplodedNodeSet Dst;
449 Dst.insert(DstI);
453 Engine.enqueue(Dst, currBldrCtx->getBlock(), currStmtIdx);
533 ExplodedNodeSet Dst;
534 NodeBuilder Bldr(Tmp, Dst, *currBldrCtx);
541 Engine.enqueue(Dst, currBldrCtx->getBlock(), currStmtIdx);
546 ExplodedNodeSet Dst;
549 ProcessAutomaticObjDtor(D.castAs<CFGAutomaticObjDtor>(), Pred, Dst);
552 ProcessBaseDtor(D.castAs<CFGBaseDtor>(), Pred, Dst);
555 ProcessMemberDtor(D.castAs<CFGMemberDtor>(), Pred, Dst);
[all...] |
| BugReporter.cpp | 617 const CFGBlock *Dst = BE->getDst();
654 if (const Stmt *S = Dst->getLabel()) {
726 if (*(Src->succ_begin()+1) == Dst)
754 if (*(Src->succ_begin()+1) == Dst) {
774 if (*(Src->succ_begin()+1) == Dst) {
795 if (*(Src->succ_begin()) == Dst) {
823 if (*(Src->succ_begin()+1) == Dst) {
853 if (*(Src->succ_begin()+1) == Dst)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | [all...] |
| /external/llvm/tools/gold/ |
| gold-plugin.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| RegisterCoalescer.cpp | 114 /// which are the src/dst of the copy instruction CopyMI. This returns
224 unsigned &Src, unsigned &Dst,
227 Dst = MI->getOperand(0).getReg();
232 Dst = MI->getOperand(0).getReg();
247 unsigned Src, Dst, SrcSub, DstSub;
248 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
252 // If one register is a physreg, it must be Dst.
254 if (TargetRegisterInfo::isPhysicalRegister(Dst))
256 std::swap(Src, Dst);
263 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
| GVN.cpp | [all...] |
| ScalarReplAggregates.cpp | 645 // Noop transfer. Src == Dst
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| IRTranslator.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 302 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | [all...] |
| /external/llvm/lib/Analysis/ |
| DependenceAnalysis.cpp | 202 return Src->mayReadFromMemory() && Dst->mayReadFromMemory();
208 return Src->mayWriteToMemory() && Dst->mayWriteToMemory();
214 return Src->mayWriteToMemory() && Dst->mayReadFromMemory();
220 return Src->mayReadFromMemory() && Dst->mayWriteToMemory();
657 // Examines the loop nesting of the Src and Dst
674 // ... - loops containing Src but not Dst
675 // SrcLevels - innermost loop containing Src but not Dst
676 // ... - loops containing Dst but not Src
677 // MaxLevels - innermost loops containing Dst but not Src
696 // to A (the Src) and the load from A (the Dst), we'll note that the
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.cpp | 144 /// src/dst of the copy instruction CopyMI. This returns true if the copy
221 /// destination (Dst) of \p Copy.
224 /// Dst is terminal if it has exactly one affinity (Dst, Src) and
225 /// at least one interference (Dst, Dst2). If Dst is terminal, the
229 /// In that case, Dst2 and Dst will not be able to be both coalesced
231 /// Dst, we can drop \p Copy.
279 unsigned &Src, unsigned &Dst,
282 Dst = MI->getOperand(0).getReg()
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 829 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
831 assert(Dst && Src && "Bad sub-register");
834 DstRegs.insert(Dst);
836 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
