/external/llvm/lib/Target/Hexagon/ |
HexagonPeephole.cpp | 105 void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src); 140 MachineOperand &Dst = MI.getOperand(0); 142 unsigned DstReg = Dst.getReg(); 158 MachineOperand &Dst = MI.getOperand(0); 163 unsigned DstReg = Dst.getReg(); 175 MachineOperand &Dst = MI.getOperand(0); 180 unsigned DstReg = Dst.getReg(); 189 MachineOperand &Dst = MI.getOperand(0); 191 unsigned DstReg = Dst.getReg(); 207 MachineOperand &Dst = MI.getOperand(0) [all...] |
RDFCopy.cpp | 33 const MachineOperand &Dst = MI->getOperand(0); 35 RegisterRef DstR = { Dst.getReg(), Dst.getSubReg() }; 58 const MachineOperand &Dst = MI->getOperand(0); 59 RegisterRef DefR = { Dst.getReg(), Dst.getSubReg() };
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/external/swiftshader/src/Pipeline/ |
VertexProgram.hpp | 61 typedef Shader::DestinationParameter Dst; 76 void M3X2(Vector4f &dst, Vector4f &src0, Src &src1); 77 void M3X3(Vector4f &dst, Vector4f &src0, Src &src1); 78 void M3X4(Vector4f &dst, Vector4f &src0, Src &src1); 79 void M4X3(Vector4f &dst, Vector4f &src0, Src &src1); 80 void M4X4(Vector4f &dst, Vector4f &src0, Src &src1); 109 void TEX(Vector4f &dst, Vector4f &src, const Src&); 110 void TEXOFFSET(Vector4f &dst, Vector4f &src, const Src&, Vector4f &offset); 111 void TEXLOD(Vector4f &dst, Vector4f &src, const Src&, Float4 &lod); 112 void TEXLODOFFSET(Vector4f &dst, Vector4f &src, const Src&, Vector4f &offset, Float4 &lod) [all...] |
/external/swiftshader/src/Shader/ |
VertexProgram.hpp | 61 typedef Shader::DestinationParameter Dst; 78 void M3X2(Vector4f &dst, Vector4f &src0, Src &src1); 79 void M3X3(Vector4f &dst, Vector4f &src0, Src &src1); 80 void M3X4(Vector4f &dst, Vector4f &src0, Src &src1); 81 void M4X3(Vector4f &dst, Vector4f &src0, Src &src1); 82 void M4X4(Vector4f &dst, Vector4f &src0, Src &src1); 112 void TEX(Vector4f &dst, Vector4f &src, const Src&); 113 void TEXOFFSET(Vector4f &dst, Vector4f &src, const Src&, Vector4f &offset); 114 void TEXLOD(Vector4f &dst, Vector4f &src, const Src&, Float4 &lod); 115 void TEXLODOFFSET(Vector4f &dst, Vector4f &src, const Src&, Vector4f &offset, Float4 &lod) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/ProfileData/ |
GCOV.cpp | 187 uint32_t Dst; 188 if (!Buff.readInt(Dst)) 190 Edges.push_back(make_unique<GCOVEdge>(*Blocks[BlockNo], *Blocks[Dst])); 193 Blocks[Dst]->addSrcEdge(Edge); 396 if (!DstEdges[DstEdgeNo]->Dst.getNumDstEdges()) 397 DstEdges[DstEdgeNo]->Dst.Counter += N; 427 OS << Edge->Dst.Number << " (" << Edge->Count << "), ";
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Support/ |
ConvertUTFWrapper.cpp | 118 UTF8 *Dst = reinterpret_cast<UTF8 *>(&Out[0]); 119 UTF8 *DstEnd = Dst + Out.size(); 122 ConvertUTF16toUTF8(&Src, SrcEnd, &Dst, DstEnd, strictConversion); 130 Out.resize(reinterpret_cast<char *>(Dst) - &Out[0]); 163 UTF16 *Dst = &DstUTF16[0]; 164 UTF16 *DstEnd = Dst + DstUTF16.size(); 167 ConvertUTF8toUTF16(&Src, SrcEnd, &Dst, DstEnd, strictConversion); 175 DstUTF16.resize(Dst - &DstUTF16[0]);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
AArch64LegalizerInfo.cpp | 412 unsigned Dst = MI.getOperand(0).getReg(); 438 uint64_t ValSize = MRI.getType(Dst).getSizeInBits() / 8; 440 Dst, DstPtr,
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AArch64AdvSIMDScalarPass.cpp | 240 unsigned Dst = MI.getOperand(0).getReg(); 243 Use = MRI->use_instr_nodbg_begin(Dst), 276 unsigned Dst, unsigned Src, bool IsKill) { 278 TII->get(AArch64::COPY), Dst) 358 unsigned Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass); 363 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), Dst) 370 insertCopy(TII, MI, MI.getOperand(0).getReg(), Dst, true);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
SIOptimizeExecMasking.cpp | 79 const MachineOperand &Dst = MI.getOperand(0); 80 if (Dst.isReg() && Dst.getReg() == AMDGPU::EXEC && MI.getOperand(1).isReg())
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
HexagonPeephole.cpp | 138 MachineOperand &Dst = MI.getOperand(0); 140 unsigned DstReg = Dst.getReg(); 156 MachineOperand &Dst = MI.getOperand(0); 161 unsigned DstReg = Dst.getReg(); 173 MachineOperand &Dst = MI.getOperand(0); 178 unsigned DstReg = Dst.getReg(); 187 MachineOperand &Dst = MI.getOperand(0); 189 unsigned DstReg = Dst.getReg(); 205 MachineOperand &Dst = MI.getOperand(0); 212 unsigned DstReg = Dst.getReg() [all...] |
RDFCopy.cpp | 45 const MachineOperand &Dst = MI->getOperand(0); 47 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg());
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/external/swiftshader/third_party/llvm-subzero/lib/Support/ |
ConvertUTFWrapper.cpp | 118 UTF8 *Dst = reinterpret_cast<UTF8 *>(&Out[0]); 119 UTF8 *DstEnd = Dst + Out.size(); 122 ConvertUTF16toUTF8(&Src, SrcEnd, &Dst, DstEnd, strictConversion); 130 Out.resize(reinterpret_cast<char *>(Dst) - &Out[0]); 163 UTF16 *Dst = &DstUTF16[0]; 164 UTF16 *DstEnd = Dst + DstUTF16.size(); 167 ConvertUTF8toUTF16(&Src, SrcEnd, &Dst, DstEnd, strictConversion); 175 DstUTF16.resize(Dst - &DstUTF16[0]);
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/device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/ |
BaseUefiTianoCustomDecompressLib.c | 744 UINT8 *Dst;
751 Dst = Destination;
785 Sd->mDstBase = Dst;
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/device/linaro/bootloader/edk2/NetworkPkg/HttpDxe/ |
HttpsSupport.c | 48 CHAR8 Dst; 67 Dst = *SearchStringTmp; 73 if ((Dst >= 'A') && (Dst <= 'Z')) { 74 Dst -= ('A' - 'a'); 77 if (Src != Dst) { [all...] |
/external/clang/lib/StaticAnalyzer/Core/ |
CoreEngine.cpp | 287 ExplodedNodeSet &Dst) { 291 Dst.Add(*I); 480 ExplodedNodeSet Dst; 481 SubEng.processBranch(Cond, Term, Ctx, Pred, Dst, 484 enqueue(Dst); 492 ExplodedNodeSet Dst; 493 SubEng.processCleanupTemporaryBranch(BTE, Ctx, Pred, Dst, *(B->succ_begin()), 496 enqueue(Dst); 503 ExplodedNodeSet Dst; 504 SubEng.processStaticInitializer(DS, Ctx, Pred, Dst, [all...] |
/external/llvm/include/llvm/ExecutionEngine/Orc/ |
OrcRemoteTargetRPCAPI.h | 30 DirectBufferWriter(const char *Src, TargetAddress Dst, uint64_t Size) 31 : Src(Src), Dst(Dst), Size(Size) {} 34 TargetAddress getDst() const { return Dst; } 39 TargetAddress Dst; 52 TargetAddress Dst; 53 if (auto EC = deserialize(C, Dst)) 58 char *Addr = reinterpret_cast<char *>(static_cast<uintptr_t>(Dst)); 60 DBW = DirectBufferWriter(0, Dst, Size); 190 void(ResourceIdMgr::ResourceId AllocID, TargetAddress Dst, [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64AdvSIMDScalarPass.cpp | 247 unsigned Dst = MI.getOperand(0).getReg(); 250 Use = MRI->use_instr_nodbg_begin(Dst), 283 unsigned Dst, unsigned Src, bool IsKill) { 285 TII->get(AArch64::COPY), Dst) 365 unsigned Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass); 370 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), Dst) 377 insertCopy(TII, MI, MI.getOperand(0).getReg(), Dst, true);
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/external/llvm/lib/Target/AMDGPU/ |
R600Packetizer.cpp | 92 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); 96 unsigned Dst = BI->getOperand(DstIdx).getReg(); 98 Result[Dst] = AMDGPU::PS; 103 Result[Dst] = AMDGPU::PV_X; 106 if (Dst == AMDGPU::OQAP) { 110 switch (TRI.getHWRegChan(Dst)) { 126 Result[Dst] = PVReg; 236 // Is the dst reg sequence legal ?
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SIFoldOperands.cpp | 343 MachineOperand &Dst = MI.getOperand(0); 344 if (Dst.isReg() && 345 !TargetRegisterInfo::isVirtualRegister(Dst.getReg()))
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/external/llvm/lib/Target/Sparc/ |
SparcInstrInfo.cpp | 375 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]); 377 assert(Dst && Src && "Bad sub-register"); 379 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(movOpc), Dst);
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/external/llvm/lib/Target/X86/ |
X86FixupLEAs.cpp | 374 const MachineOperand &Dst = MI.getOperand(0); 380 .addOperand(Dst) 390 .addOperand(Dst)
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/external/llvm/unittests/Linker/ |
LinkModulesTest.cpp | 281 auto Dst = llvm::make_unique<Module>("Linked", C); 282 ASSERT_TRUE(Dst.get()); 284 Linker::linkModules(*Dst, std::move(Src)); 288 F = &*Dst->begin(); 292 NMD = &*Dst->named_metadata_begin(); 350 auto Dst = llvm::make_unique<Module>("Linked", C); 351 ASSERT_TRUE(Dst.get());
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/external/mesa3d/src/gallium/auxiliary/tgsi/ |
tgsi_parse.h | 94 struct tgsi_full_dst_register Dst[TGSI_FULL_MAX_DST_REGISTERS];
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/external/swiftshader/third_party/LLVM/lib/ExecutionEngine/JIT/ |
JITDwarfEmitter.cpp | 85 const MachineLocation &Dst = Move.getDestination(); 98 if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) { 113 if (Dst.isReg()) { 115 JCE->emitULEB128Bytes(RI->getDwarfRegNum(Dst.getReg(), true)); 121 int Offset = Dst.getOffset() / stackGrowth;
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/ExecutionEngine/Orc/ |
OrcRemoteTargetRPCAPI.h | 62 DirectBufferWriter(const char *Src, JITTargetAddress Dst, uint64_t Size) 63 : Src(Src), Dst(Dst), Size(Size) {} 66 JITTargetAddress getDst() const { return Dst; } 71 JITTargetAddress Dst; 125 JITTargetAddress Dst; 126 if (auto EC = deserializeSeq(C, Dst)) 131 char *Addr = reinterpret_cast<char *>(static_cast<uintptr_t>(Dst)); 133 DBW = remote::DirectBufferWriter(nullptr, Dst, Size); 260 JITTargetAddress Dst, uint32_t ProtFlags)> [all...] |