/frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
scale_sig_neon.s | 101 VSHLL.S16 Q10, D8, #16
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/external/google-breakpad/src/common/ |
stabs_reader_unittest.cc | 153 D8(type); 154 D8(other);
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test_assembler_unittest.cc | 1174 section.D8(0xe6U); 1183 section.D8(l); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
AArch64BaseInfo.h | 120 case AArch64::D8: return AArch64::B8; 160 case AArch64::B8: return AArch64::D8;
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
ARMBaseRegisterInfo.cpp | 78 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 89 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 726 case ARM::D9: return ARM::D8; 779 case ARM::D8: return ARM::D9; [all...] |
/external/swiftshader/third_party/LLVM/utils/TableGen/ |
X86RecognizableInstr.cpp | 67 D8 = 3, D9 = 4, DA = 5, DB = 6, 878 case X86Local::D8: 895 opcodeToSet = 0xd8 + (Prefix - X86Local::D8); [all...] |
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
ARMGenRegisterInfo.inc | 42 D8 = 22, [all...] |
/external/google-breakpad/src/common/dwarf/ |
dwarf2reader_die_unittest.cc | 177 .D8(0); // end of children
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/external/llvm/lib/Target/AArch64/ |
AArch64PBQPRegAlloc.cpp | 117 case AArch64::D8:
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
AArch64AsmBackend.cpp | 486 // D8/D9 pair = 0x00000100, 490 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 &&
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
MipsRegisterInfo.cpp | 95 case Mips::D8:
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
AArch64PBQPRegAlloc.cpp | 117 case AArch64::D8:
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/external/libhevc/common/arm/ |
ihevc_sao_edge_offset_class1.s | 82 vpush {d8 - d15} 135 VLD1.8 D8,[r9]! @pu1_top_row = vld1q_u8(pu1_src_top_cpy || pu1_src - src_strd) 279 VLD1.8 D8,[r9]! @pu1_top_row = vld1q_u8(pu1_src_top_cpy || pu1_src - src_strd) 375 vpop {d8 - d15}
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ihevc_sao_edge_offset_class2_chroma.s | 98 vpush {d8 - d15} 317 VMOV.8 D8[0],r8 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0) 320 VMOV.8 D8[1],r8 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0) [all...] |
ihevc_sao_edge_offset_class3_chroma.s | 98 vpush {d8 - d15} 311 VMOV.8 D8[0],r8 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0) 315 VMOV.8 D8[1],r8 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0) [all...] |
/external/libvpx/libvpx/ |
libs.mk | 460 --proj-guid=CD837F5F-52D8-4314-A370-895D614166A7 \ 482 --proj-guid=CD837F5F-52D8-4314-A370-895D614166A7 \
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/external/libxaac/decoder/armv7/ |
ixheaacd_sbr_imdct_using_fft.s | 29 VPUSH {D8 - D15} 114 VLD2.32 {d8[0], d10[0]}, [r5] , r1 125 VLD2.32 {d8[1], d10[1]}, [r6] , r1 435 VSWP d15, d8 509 VLD2.32 {d8[0], d10[0]}, [r5] , r1 520 VLD2.32 {d8[1], d10[1]}, [r6] , r1 853 VPOP {D8 - D15}
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ixheaacd_tns_ar_filter_fixed.s | 32 vpush {d8-d15} 133 VLD1.32 {D8, D9}, [R12]! 320 VMLAL.S32 Q1, D8, D4 @order20 552 vpop {d8-d15}
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
HexagonMCInstrInfo.cpp | 213 case D8: 441 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
X86CodeEmitter.cpp | 680 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: 683 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/Disassembler/ |
HexagonDisassembler.cpp | 640 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 650 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
HexagonMCInstrInfo.cpp | 250 case D8: 563 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
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/external/fonttools/Lib/fontTools/ |
agl.py | 227 00D8;Oslash;LATIN CAPITAL LETTER O WITH STROKE 376 02D8;breve;BREVE 497 25D8;invbullet;INVERSE BULLET [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
AArch64AsmBackend.cpp | 543 // D8/D9 pair = 0x00000100, 547 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 &&
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/external/antlr/runtime/Delphi/Sources/Antlr3.Runtime.Tests/ |
Antlr.Runtime.Tools.Tests.pas | 111 ['{48E3FC72-4E63-46D8-8450-A561ECF76995}']
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