| /external/llvm/test/MC/Mips/mips32r6/ |
| valid.s | 17 # FIXME: Add the instructions carried forward from older ISA's
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| valid.s | 17 # FIXME: Add the instructions carried forward from older ISA's
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r6/ |
| valid.s | 17 # FIXME: Add the instructions carried forward from older ISA's
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r6/ |
| valid.s | 17 # FIXME: Add the instructions carried forward from older ISA's
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/ |
| invalid-mips4-wrong-error.s | 9 bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
10 bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
|
| /external/llvm/test/MC/Mips/ |
| mips_abi_flags_xx.s | 41 # CHECK-OBJ-32R1-NEXT: ISA: {{MIPS32$}}
42 # CHECK-OBJ-32R6-NEXT: ISA: MIPS32r6
43 # CHECK-OBJ-64R2-NEXT: ISA: MIPS64r2
44 # CHECK-OBJ-MIPS-NEXT: ISA Extension: None (0x0)
45 # CHECK-OBJ-OCTEON-NEXT: ISA Extension: Cavium Networks Octeon (0x5)
|
| mips_abi_flags_xx_set.s | 30 # CHECK-OBJ-NEXT: ISA: {{MIPS32$}}
31 # CHECK-OBJ-NEXT: ISA Extension: None (0x0)
|
| set-push-pop-directives.s | 20 .set mips32r6 # Test the Features option (ISA).
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| mips_abi_flags_xx.s | 41 # CHECK-OBJ-32R1-NEXT: ISA: {{MIPS32$}}
42 # CHECK-OBJ-32R6-NEXT: ISA: MIPS32r6
43 # CHECK-OBJ-64R2-NEXT: ISA: MIPS64r2
44 # CHECK-OBJ-MIPS-NEXT: ISA Extension: None (0x0)
45 # CHECK-OBJ-OCTEON-NEXT: ISA Extension: Cavium Networks Octeon (0x5)
|
| mips_abi_flags_xx_set.s | 30 # CHECK-OBJ-NEXT: ISA: {{MIPS32$}}
31 # CHECK-OBJ-NEXT: ISA Extension: None (0x0)
|
| set-push-pop-directives.s | 20 .set mips32r6 # Test the Features option (ISA).
|
| /external/archive-patcher/generator/src/main/java/com/google/archivepatcher/generator/bsdiff/ |
| DivSuffixSorter.java | [all...] |
| /external/ImageMagick/PerlMagick/ |
| Magick.pm | 22 use vars qw($VERSION @ISA @EXPORT $AUTOLOAD);
29 @ISA = qw(Exporter DynaLoader);
|
| /external/ImageMagick/PerlMagick/quantum/ |
| quantum.pm | 21 use vars qw($VERSION @ISA @EXPORT $AUTOLOAD);
28 @ISA = qw(Exporter DynaLoader);
|
| /external/curl/tests/ |
| serverhelp.pm | 34 @ISA
42 @ISA = qw(Exporter);
|
| sshhelp.pm | 35 @ISA
63 @ISA = qw(Exporter);
|
| /external/llvm/lib/Target/Mips/ |
| MipsSubtarget.cpp | 109 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
114 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
|
| /external/llvm/test/MC/ELF/ |
| discriminator.s | 59 # DWARF-DUMP: Address Line Column File ISA Discriminator Flags
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ELF/ |
| discriminator.s | 59 # DWARF-DUMP: Address Line Column File ISA Discriminator Flags
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsSubtarget.cpp | 133 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
138 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
|
| /external/clang/lib/CodeGen/ |
| CGDeclCXX.cpp | 299 InitSegAttr *ISA) {
303 PtrArray->setSection(ISA->getSection());
344 auto *ISA = D->getAttr<InitSegAttr>();
360 } else if (PerformInit && ISA) {
361 EmitPointerToInitFunc(D, Addr, Fn, ISA);
|
| /external/libdivsufsort/include/ |
| divsufsort_private.h | 200 trsort(saidx_t *ISA, saidx_t *SA, saidx_t n, saidx_t depth);
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUAsmPrinter.cpp | 111 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI->getFeatureBits());
112 TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| implicit-it-generation.s | 108 @ Flush on an ISA change (even to the same ISA)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/RISCV/ |
| rvf-aliases-valid.s | 23 ## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
46 # The following instructions actually alias instructions from the base ISA.
|
