| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| AMDGPUAsmParser.cpp | 216 return isa<MCSymbolRefExpr>(Expr);
923 AMDGPU::IsaInfo::IsaVersion ISA =
926 if (ISA.Major >= 6 && AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) {
929 Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));
933 Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));
935 Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));
937 Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));
939 if (ISA.Major >= 6 && AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) {
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Utils/ |
| AMDGPUBaseInfo.cpp | 419 IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(Features);
426 Header.amd_machine_version_major = ISA.Major;
427 Header.amd_machine_version_minor = ISA.Minor;
428 Header.amd_machine_version_stepping = ISA.Stepping;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.cpp | [all...] |
| /external/boringssl/src/crypto/fipsmodule/modes/asm/ |
| ghash-armv4.pl | 295 bx lr @ interoperable with Thumb ISA:-)
378 bx lr @ interoperable with Thumb ISA:-)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/RISCV/ |
| rvd-aliases-valid.s | 23 ## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
|
| /external/curl/tests/ |
| pathhelp.pm | 59 our @ISA = qw(Exporter);
|
| /external/llvm/lib/Support/ |
| Triple.cpp | 292 unsigned ISA = ARM::parseArchISA(ArchName);
298 switch (ISA) {
312 switch (ISA) {
332 if (ISA == ARM::IK_THUMB &&
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| AMDGPUAsmPrinter.cpp | 138 IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
140 ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
153 // Emit ISA Version (NT_AMD_AMDGPU_ISA).
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-dwarfdump/X86/ |
| brief.s | 19 # CHECK: Address Line Column File ISA Discriminator Flags
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Support/ |
| Triple.cpp | 316 ARM::ISAKind ISA = ARM::parseArchISA(ArchName);
322 switch (ISA) {
338 switch (ISA) {
363 if (ISA == ARM::ISAKind::THUMB &&
[all...] |
| /external/swiftshader/third_party/llvm-subzero/lib/Support/ |
| Triple.cpp | 305 unsigned ISA = ARM::parseArchISA(ArchName);
311 switch (ISA) {
325 switch (ISA) {
345 if (ISA == ARM::IK_THUMB &&
[all...] |
| /external/capstone/bindings/vb6/ |
| Module1.bas | 39 CS_MODE_MIPS3 = 32 ' Mips III ISA
40 CS_MODE_MIPS32R6 = 64 ' Mips32r6 ISA
44 CS_MODE_MIPS32 = CS_MODE_32 ' Mips32 ISA (Mips)
45 CS_MODE_MIPS64 = CS_MODE_64 ' Mips64 ISA (Mips)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/ |
| invalid-mips4.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
|
| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| aes-armv4.S | 34 @ by gcc-3.4.1. This is thanks to unique feature of ARMv4 ISA, which
293 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
741 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
859 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
1078 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
| armv4-mont.S | 210 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
| ghash-armv4.S | 228 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
371 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| aes-armv4.S | 35 @ by gcc-3.4.1. This is thanks to unique feature of ARMv4 ISA, which
292 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
736 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
850 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
1067 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
| armv4-mont.S | 209 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
| ghash-armv4.S | 225 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
366 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
| /external/boringssl/src/crypto/fipsmodule/aes/asm/ |
| aes-armv4.pl | 22 # by gcc-3.4.1. This is thanks to unique feature of ARMv4 ISA, which
309 bx lr @ interoperable with Thumb ISA:-)
752 bx lr @ interoperable with Thumb ISA:-)
869 bx lr @ interoperable with Thumb ISA:-)
1085 bx lr @ interoperable with Thumb ISA:-)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips1/ |
| invalid-mips4.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
|
| invalid-mips5.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
|
| /external/boringssl/src/crypto/fipsmodule/bn/asm/ |
| armv4-mont.pl | 29 # The code is interoperable with Thumb ISA and is rather compact, less
293 bx lr @ interoperable with Thumb ISA:-)
|
| /external/boringssl/src/crypto/fipsmodule/sha/asm/ |
| sha1-armv4-large.pl | 303 bx lr @ interoperable with Thumb ISA:-)
|
| sha256-armv4.pl | 299 bx lr @ interoperable with Thumb ISA:-)
|
