| /external/deqp-deps/SPIRV-Headers/example/ |
| example.cpp | 35 const spv::Op kNop = spv::OpNop;
|
| /external/deqp-deps/glslang/SPIRV/ |
| GLSL.ext.NV.h | 32 enum Op;
|
| /external/shaderc/spirv-headers/example/ |
| example.cpp | 35 const spv::Op kNop = spv::OpNop;
|
| /external/skia/fuzz/ |
| FuzzRegionOp.cpp | 15 SkRegion::Op op; local
16 fuzz->nextRange(&op, 0, SkRegion::kLastOp);
17 regionC.op(regionA, regionB, op);
|
| /external/skia/src/gpu/glsl/ |
| GrGLSLBlend.h | 25 const char* dstColor, const char* outColor, SkRegion::Op regionOp);
|
| /external/skqp/fuzz/ |
| FuzzRegionOp.cpp | 15 SkRegion::Op op; local
16 fuzz->nextRange(&op, 0, SkRegion::kLastOp);
17 regionC.op(regionA, regionB, op);
|
| /external/skqp/src/gpu/glsl/ |
| GrGLSLBlend.h | 25 const char* dstColor, const char* outColor, SkRegion::Op regionOp);
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86AsmPrinter.h | 70 void printSSECC(const MachineInstr *MI, unsigned Op, raw_ostream &O);
71 void printMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
73 void printLeaMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
76 void printPICLabel(const MachineInstr *MI, unsigned Op, raw_ostream &O);
|
| X86InstrInfo.h | 109 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
110 if (MI->getOperand(Op).isFI()) return true;
111 return Op+4 <= MI->getNumOperands() &&
112 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
113 MI->getOperand(Op+2).isReg() &&
114 (MI->getOperand(Op+3).isImm() ||
115 MI->getOperand(Op+3).isGlobal() ||
116 MI->getOperand(Op+3).isCPI() ||
117 MI->getOperand(Op+3).isJTI())
[all...] |
| /external/swiftshader/third_party/SPIRV-Headers/example/ |
| example.cpp | 35 const spv::Op kNop = spv::OpNop;
|
| /external/syzkaller/vendor/google.golang.org/grpc/naming/ |
| naming.go | 42 // Op indicates the operation of the update.
43 Op Operation
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 80 const MCOperand &Op = MI->getOperand(OpNo);
81 if (Op.isReg()) {
82 printRegName(O, Op.getReg());
86 if (Op.isImm()) {
87 O << Op.getImm();
91 assert(Op.isExpr() && "unknown operand kind in printOperand");
92 O << *Op.getExpr();
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelLowering.h | 285 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
295 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
330 virtual void LowerAsmOperandForConstraint(SDValue Op,
386 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
387 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
388 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
389 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
390 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
391 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
392 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| ARCISelLowering.h | 67 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
88 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| MCDwarf.h | 240 MCCFIInstruction(OpType Op, MCSymbol *L)
241 : Operation(Op), Label(L) {
242 assert(Op == Remember || Op == Restore);
244 MCCFIInstruction(OpType Op, MCSymbol *L, unsigned Register)
245 : Operation(Op), Label(L), Destination(Register) {
246 assert(Op == SameValue);
252 MCCFIInstruction(OpType Op, MCSymbol *L, const MachineLocation &D,
254 : Operation(Op), Label(L), Destination(D), Source(S) {
255 assert(Op == RelMove)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 44 unsigned Op;
46 Op = NVPTX::IMOV1rr;
48 Op = NVPTX::IMOV16rr;
50 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
53 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
56 Op = (SrcRC == &NVPTX::Float16RegsRegClass ? NVPTX::FMOV16rr
59 Op = NVPTX::IMOV32rr;
61 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
64 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
69 BuildMI(MBB, I, DL, get(Op), DestReg
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.h | 87 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
88 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
94 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
95 SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const;
96 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| DivZeroChecker.cpp | 50 BinaryOperator::Opcode Op = B->getOpcode();
51 if (Op != BO_Div &&
52 Op != BO_Rem &&
53 Op != BO_DivAssign &&
54 Op != BO_RemAssign)
|
| /external/skia/src/gpu/ |
| GrMemoryPool.h | 137 template <typename Op, typename... OpArgs>
138 std::unique_ptr<Op> allocate(OpArgs&&... opArgs) {
139 char* mem = (char*) fMemoryPool.allocate(sizeof(Op));
140 return std::unique_ptr<Op>(new (mem) Op(std::forward<OpArgs>(opArgs)...));
147 void release(std::unique_ptr<GrOp> op);
|
| /external/skqp/src/gpu/ |
| GrMemoryPool.h | 137 template <typename Op, typename... OpArgs>
138 std::unique_ptr<Op> allocate(OpArgs&&... opArgs) {
139 char* mem = (char*) fMemoryPool.allocate(sizeof(Op));
140 return std::unique_ptr<Op>(new (mem) Op(std::forward<OpArgs>(opArgs)...));
147 void release(std::unique_ptr<GrOp> op);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfExpression.cpp | 219 auto Op = ExprCursor.peek();
220 if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
247 [](DIExpression::ExprOperand Op) -> bool {
248 return Op.getOp() == dwarf::DW_OP_stack_value;
263 if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
264 SignedOffset = Op->getArg(0);
271 if (Op && Op->getOp() == dwarf::DW_OP_constu)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 176 SDValue LanaiTargetLowering::LowerOperation(SDValue Op,
178 switch (Op.getOpcode()) {
180 return LowerMUL(Op, DAG);
182 return LowerBR_CC(Op, DAG);
184 return LowerConstantPool(Op, DAG);
186 return LowerGlobalAddress(Op, DAG);
188 return LowerBlockAddress(Op, DAG);
190 return LowerJumpTable(Op, DAG);
192 return LowerSELECT_CC(Op, DAG);
194 return LowerSETCC(Op, DAG)
[all...] |
| /cts/tests/tests/graphics/src/android/graphics/cts/ |
| RegionTest.java | 347 assertFalse(mRegion.op(rect1, Region.Op.DIFFERENCE));
348 assertFalse(mRegion.op(rect1, Region.Op.INTERSECT));
349 assertFalse(mRegion.op(rect1, Region.Op.UNION));
350 assertFalse(mRegion.op(rect1, Region.Op.XOR));
351 assertFalse(mRegion.op(rect1, Region.Op.REVERSE_DIFFERENCE))
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 161 SDValue LanaiTargetLowering::LowerOperation(SDValue Op,
163 switch (Op.getOpcode()) {
165 return LowerMUL(Op, DAG);
167 return LowerBR_CC(Op, DAG);
169 return LowerConstantPool(Op, DAG);
171 return LowerGlobalAddress(Op, DAG);
173 return LowerBlockAddress(Op, DAG);
175 return LowerJumpTable(Op, DAG);
177 return LowerSELECT_CC(Op, DAG);
179 return LowerSETCC(Op, DAG)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMISelLowering.h | 242 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
300 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
305 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
330 virtual void LowerAsmOperandForConstraint(SDValue Op,
403 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
404 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
405 SDValue LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) const;
406 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
408 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
409 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const
[all...] |
