| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcISelLowering.h | 47 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
52 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
96 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
97 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonExpandCondsets.cpp | 178 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
179 Sub(Op.getSubReg()) {}
320 MachineOperand &Op = MI->getOperand(i);
321 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg ||
324 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg());
328 Op.setIsKill(true);
373 auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> std::pair<bool,bool>
[all...] |
| HexagonISelLoweringHVX.cpp | 204 for (const SDValue &Op : Ops)
205 IntOps.push_back(Op);
[all...] |
| /external/libcxx/test/std/input.output/filesystems/class.directory_entry/directory_entry.obs/ |
| comparisons.pass.cpp | 29 #define CHECK_OP(Op) \
30 static_assert(std::is_same<decltype(ce. operator Op (ce)), bool>::value, ""); \
31 static_assert(noexcept(ce.operator Op (ce)), "Operation must be noexcept" )
|
| /external/llvm/lib/IR/ |
| IntrinsicInst.cpp | 36 Value *Op = getArgOperand(0);
37 if (AllowNullOp && !Op)
40 auto *MD = cast<MetadataAsValue>(Op)->getMetadata();
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsELFStreamer.cpp | 26 const MCOperand &Op = Inst.getOperand(OpIndex);
28 if (!Op.isReg())
31 unsigned Reg = Op.getReg();
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelDAGToDAG.cpp | 59 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
98 const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
104 OutOps.push_back(Op);
|
| /external/llvm/lib/Transforms/ObjCARC/ |
| DependencyAnalysis.cpp | 59 const Value *Op = *I;
60 if (IsPotentialRetainableObjPtr(Op, *PA.getAA()) &&
61 PA.related(Ptr, Op, DL))
106 const Value *Op = *OI;
107 if (IsPotentialRetainableObjPtr(Op, *PA.getAA()) &&
108 PA.related(Ptr, Op, DL))
115 const Value *Op = GetUnderlyingObjCPtr(SI->getPointerOperand(), DL);
118 return IsPotentialRetainableObjPtr(Op, *PA.getAA()) &&
119 PA.related(Op, Ptr, DL);
125 const Value *Op = *OI
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXISelLowering.h | 44 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
46 virtual SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
81 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| AVRISelLowering.h | 85 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
98 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
123 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
133 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
136 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
137 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelDAGToDAG.cpp | 59 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
92 const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
98 OutOps.push_back(Op);
|
| WebAssemblyISelLowering.cpp | 88 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM,
90 setOperationAction(Op, T, Expand);
93 for (auto Op :
95 setOperationAction(Op, T, Legal);
108 for (auto Op :
113 setOperationAction(Op, T, Expand);
135 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
136 setOperationAction(Op, T, Expand);
723 SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
725 SDLoc DL(Op);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/ObjCARC/ |
| DependencyAnalysis.cpp | 59 const Value *Op = *I;
60 if (IsPotentialRetainableObjPtr(Op, *PA.getAA()) &&
61 PA.related(Ptr, Op, DL))
106 const Value *Op = *OI;
107 if (IsPotentialRetainableObjPtr(Op, *PA.getAA()) &&
108 PA.related(Ptr, Op, DL))
115 const Value *Op = GetUnderlyingObjCPtr(SI->getPointerOperand(), DL);
118 return IsPotentialRetainableObjPtr(Op, *PA.getAA()) &&
119 PA.related(Op, Ptr, DL);
125 const Value *Op = *OI
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/ |
| BenchmarkRunner.cpp | 154 const auto GetOpReg = [&II](const Operand &Op) -> unsigned {
155 if (Op.ImplicitReg) {
156 return *Op.ImplicitReg;
157 } else if (Op.IsExplicit && II.getValueFor(Op).isReg()) {
158 return II.getValueFor(Op).getReg();
163 for (const Operand &Op : II.Instr.Operands) {
164 if (!Op.IsDef) {
165 const unsigned Reg = GetOpReg(Op);
173 for (const Operand &Op : II.Instr.Operands)
[all...] |
| /external/tensorflow/tensorflow/go/ |
| operation.go | 34 func (op *Operation) Name() string {
35 return C.GoString(C.TF_OperationName(op.c))
39 func (op *Operation) Type() string {
40 return C.GoString(C.TF_OperationOpType(op.c))
43 // NumOutputs returns the number of outputs of op.
44 func (op *Operation) NumOutputs() int {
45 return int(C.TF_OperationNumOutputs(op.c))
50 func (op *Operation) Device() string {
51 return C.GoString(C.TF_OperationDevice(op.c))
55 // named output of op
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 413 // 3-op Variable Permute (VPERMT2).
417 // 3-op Variable Permute overwriting the index (VPERMI2).
718 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
746 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
775 void computeKnownBitsForTargetNode(const SDValue Op,
782 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
806 void LowerAsmOperandForConstraint(SDValue Op,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
| Reassociate.cpp | 51 Value *Op;
52 ValueEntry(unsigned R, Value *O) : Rank(R), Op(O) {}
65 << *Ops[0].Op->getType() << '\t';
68 WriteAsOperand(dbgs(), Ops[i].Op, false, M);
118 Instruction *Op = dyn_cast<Instruction>(V);
119 if (!Op || !isa<BinaryOperator>(Op))
122 Value *LHS = Op->getOperand(0), *RHS = Op->getOperand(1);
124 ValueRankMap.erase(Op);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 92 SDValue Op(Node, ResNo);
94 VRBaseMap.erase(Op);
95 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
125 SDValue Op = User->getOperand(i);
126 if (Op.getNode() != Node || Op.getResNo() != ResNo)
128 MVT VT = Node->getSimpleValueType(Op.getResNo());
182 SDValue Op(Node, ResNo);
184 VRBaseMap.erase(Op);
185 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 78 << *Ops[0].Op->getType() << '\t';
81 Ops[i].Op->printAsOperand(dbgs(), false, M);
274 Neg->setOperand(1, Constant::getNullValue(Ty)); // Drop use of op.
294 /// The existing weight LHS represents the computation X op X op ... op X where
295 /// X occurs LHS times. The combined weight represents X op X op ... op X with
296 /// X occurring LHS + RHS times. If op is "Xor" for example then the combine
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.h | 146 SDValue BitConvertToInteger(SDValue Op);
147 SDValue BitConvertVectorToIntegerVector(SDValue Op);
148 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
170 void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
171 void SplitInteger(SDValue Op, EVT LoVT, EVT HiVT,
178 /// GetPromotedInteger - Given a processed operand Op which was promoted to a
180 /// promoted value corresponding to the original type are exactly equal to Op.
184 /// For example, if Op is an i16 and was promoted to an i32, then this method
185 /// returns an i32, the lower 16 bits of which coincide with Op, and the upper
187 SDValue GetPromotedInteger(SDValue Op) {
[all...] |
| TargetLowering.cpp | 638 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
640 switch (Op) {
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 66 // Add pseudo op to model memcpy for struct byval.
285 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
383 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
387 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
412 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
612 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
634 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
635 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
636 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
637 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG
[all...] |
| /external/tensorflow/tensorflow/compiler/jit/ |
| build_xla_ops_pass_test.cc | 53 using ::tensorflow::testing::matchers::Op;
150 EXPECT_THAT(write_op_new, NodeWith(CtrlDeps(NodeWith(Op("_XlaRun")))));
186 auto xla_compile = NodeWith(Op("_XlaCompile"), Attr("must_compile", false));
188 NodeWith(Op("Switch"), Inputs(Out(0, xla_compile), Out(1, xla_compile)));
190 NodeWith(Op("_XlaRun"), Inputs(Out(1, predicated_compilation_key)));
192 NodeWith(Op("PartitionedCall"),
193 CtrlDeps(NodeWith(Op("Identity"),
195 auto merge = NodeWith(Op("Merge"), Inputs(Out(tf_call), Out(xla_run)));
196 auto assign_var = NodeWith(Op("AssignVariableOp"), Inputs(_, Out(merge)));
225 NodeWith(Op("_XlaRun"), Inputs(Out(NodeWith(Op("_XlaCompile")))))
[all...] |
| increase_dynamism_for_auto_jit_pass_test.cc | 38 using testing::matchers::Op;
118 auto m_input = Out(NodeWith(Op("Placeholder"), Name("input")));
120 Op("Cast"), Inputs(Out(NodeWith(Op("Placeholder"), Name("begin"))))));
121 auto m_input_shape = Out(NodeWith(Op("Shape"), Inputs(m_input)));
123 Op("Sub"), AssignedDevice(kHostName),
125 Out(NodeWith(Op("Slice"), AssignedDevice(kHostName),
127 Out(NodeWith(Op("Slice"), AssignedDevice(kHostName),
130 Op("ConcatV2"), AssignedDevice(kHostName),
136 Op("Slice"), AssignedDevice(kDeviceName)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 92 SDValue Op(Node, ResNo);
94 VRBaseMap.erase(Op);
95 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
125 SDValue Op = User->getOperand(i);
126 if (Op.getNode() != Node || Op.getResNo() != ResNo)
128 MVT VT = Node->getSimpleValueType(Op.getResNo());
181 SDValue Op(Node, ResNo);
183 VRBaseMap.erase(Op);
184 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second
[all...] |
