| /external/swiftshader/third_party/subzero/src/ |
| PNaClTranslator.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 743 /// Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all
744 /// elements. VT must be a vector type. Op's type must be the same as (or,
746 SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op) {
748 if (Op.getOpcode() == ISD::UNDEF) {
749 assert((VT.getVectorElementType() == Op.getValueType() ||
751 VT.getVectorElementType().bitsLE(Op.getValueType()))) &&
757 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Op);
767 /// Convert Op, which must be of float type, to the
769 SDValue getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT);
771 /// Convert Op, which must be of integer type, to th
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonBlockRanges.cpp | 312 for (auto &Op : In.operands()) {
313 if (!Op.isReg() || !Op.isUse() || Op.isUndef())
315 RegisterRef R = { Op.getReg(), Op.getSubReg() };
318 bool IsKill = Op.isKill();
326 for (auto &Op : In.operands()) {
327 if (!Op.isReg() || !Op.isDef() || Op.isUndef()
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| ConstantFolding.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/AsmParser/ |
| AVRAsmParser.cpp | 72 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
268 AVROperand const &Op = (AVROperand const &)*Operands[ErrorInfo];
271 if (Op.getStartLoc() != SMLoc()) {
272 ErrorLoc = Op.getStartLoc();
676 AVROperand &Op = static_cast<AVROperand &>(AsmOp);
681 if (Op.isImm()) {
682 if (MCConstantExpr const *Const = dyn_cast<MCConstantExpr>(Op.getImm())) {
688 Op.makeReg(RegNum);
689 if (validateOperandClass(Op, Expected) == Match_Success) {
697 if (Op.isReg())
[all...] |
| /external/clang/lib/Index/ |
| IndexBody.cpp | 105 OverloadedOperatorKind Op = CXXOp->getOperator();
106 if (Op == OO_Equal) {
108 } else if ((Op >= OO_PlusEqual && Op <= OO_PipeEqual) ||
109 Op == OO_LessLessEqual || Op == OO_GreaterGreaterEqual ||
110 Op == OO_PlusPlus || Op == OO_MinusMinus) {
113 } else if (Op == OO_Amp) {
|
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 585 virtual bool canOpTrap(unsigned Op, EVT VT) const;
598 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
602 if (Op > array_lengthof(OpActions[0])) return Custom;
603 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
609 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
611 (getOperationAction(Op, VT) == Legal ||
612 getOperationAction(Op, VT) == Custom);
618 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
620 (getOperationAction(Op, VT) == Legal ||
621 getOperationAction(Op, VT) == Promote)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 106 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
114 bool tryIndexedLoad(SDNode *Op);
115 bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
283 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
289 if (!SelectAddr(Op, Op0, Op1))
351 bool MSP430DAGToDAGISel::tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
355 IsLegalToFold(N1, Op, Op, OptLevel)) {
366 CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
|
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.cpp | 238 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
401 const MCOperand &Op = MI->getOperand(OpNo);
402 const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
434 const MCOperand &Op = MI->getOperand(OpNo);
435 if (Op.isReg()) {
436 const char *RegName = getRegisterName(Op.getReg());
445 if (Op.isImm()) {
446 O << Op.getImm();
450 assert(Op.isExpr() && "unknown operand kind in printOperand");
451 Op.getExpr()->print(O, &MAI)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 111 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
119 SDNode *SelectIndexedLoad(SDNode *Op);
120 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
286 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
292 if (!SelectAddr(Op, Op0, Op1))
353 SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op,
358 IsLegalToFold(N1, Op, Op, OptLevel)) {
369 CurDAG->SelectNodeTo(Op, Opc,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 109 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
117 bool tryIndexedLoad(SDNode *Op);
118 bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
286 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
292 if (!SelectAddr(Op, Op0, Op1))
354 bool MSP430DAGToDAGISel::tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
358 IsLegalToFold(N1, Op, Op, OptLevel)) {
369 CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/ |
| InstrBuilder.cpp | 191 const MCOperand &Op = MCI.getOperand(i);
192 if (!Op.isReg())
254 const MCOperand &Op = MCI.getOperand(MCI.getNumOperands() - 1);
255 if (i == MCI.getNumOperands() || !Op.isReg())
278 const MCOperand &Op = MCI.getOperand(i);
279 if (Op.isReg())
415 const MCOperand &Op = MCI.getOperand(RD.OpIndex);
417 if (!Op.isReg())
419 RegID = Op.getReg();
|
| /cts/tests/tests/graphics/src/android/graphics/cts/ |
| RegionIteratorTest.java | 68 region.op(rect, Region.Op.UNION);
95 region.op(rect, Region.Op.DIFFERENCE);
117 region.op(rect, Region.Op.INTERSECT);
134 region.op(rect, Region.Op.REVERSE_DIFFERENCE);
156 region.op(rect, Region.Op.XOR)
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFixIrreducibleControlFlow.cpp | 251 for (auto &Op : Term.explicit_uses())
252 if (Op.isMBB() && Indices.count(Op.getMBB()))
253 Op.setMBB(Map[Op.getMBB()]);
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.h | 42 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
43 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
44 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
49 void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS);
50 void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &OS);
|
| X86IntelInstPrinter.h | 37 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
38 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O);
39 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &O);
44 void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS);
45 void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O);
|
| /external/spirv-llvm/lib/SPIRV/ |
| OCL21ToSPIRV.cpp | 70 // __spirv{N}Op{ConvertOpName}(src, dummy)
73 void visitCallConvert(CallInst *CI, StringRef MangledName, Op OC);
77 /// y = __spirv{N}Op{Decorate}(x, type, value, dummy)
90 void transBuiltin(CallInst *CI, Op OC);
163 Op OC = OpNop;
180 StringRef MangledName, Op OC) {
223 OCL21ToSPIRV::transBuiltin(CallInst* CI, Op OC) {
|
| /external/swiftshader/third_party/LLVM/lib/Transforms/Utils/ |
| ValueMapper.cpp | 65 Value *OP = MD->getOperand(i);
66 if (OP == 0 || MapValue(OP, VM, Flags, TypeMapper) == OP) continue;
72 Value *Op = MD->getOperand(i);
73 Elts.push_back(Op ? MapValue(Op, VM, Flags, TypeMapper) : 0);
108 Value *Op = C->getOperand(OpNo);
109 Mapped = MapValue(Op, VM, Flags, TypeMapper);
163 for (User::op_iterator op = I->op_begin(), E = I->op_end(); op != E; ++op)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/Disassembler/ |
| BPFDisassembler.cpp | 201 auto& Op = Instr.getOperand(1);
202 Op.setImm(Make_64(Hi, Op.getImm()));
211 auto Op = Instr.getOperand(0);
214 Instr.addOperand(Op);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonCopyToCombine.cpp | 176 const MachineOperand &Op = I.getOperand(1);
177 return !Op.isImm() || !isInt<N>(Op.getImm());
240 MachineOperand &Op = MI.getOperand(I);
241 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
243 Op.setIsKill(false);
407 MachineOperand &Op = MI.getOperand(OpdIdx);
410 if (!Op.isReg() || !Op.isUse() || !Op.getReg()
[all...] |
| RDFDeadCode.cpp | 66 for (auto &Op : MI->operands()) {
67 if (Op.isReg() && MRI.isReserved(Op.getReg()))
69 if (Op.isRegMask()) {
70 const uint32_t *BM = Op.getRegMask();
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFixIrreducibleControlFlow.cpp | 254 for (auto &Op : Term.explicit_uses())
255 if (Op.isMBB() && Indices.count(Op.getMBB()))
256 Op.setMBB(Map[Op.getMBB()]);
|
| /external/tensorflow/tensorflow/core/ops/ |
| debug_ops.cc | 18 #include "tensorflow/core/framework/op.h"
37 Copy Op.
45 Unlike the CopyHost Op, this op does not have HostMemory constraint on its
51 debug_ops_spec: A list of debug op spec (op, url, gated_grpc) for attached debug
67 Copy Host Op.
74 Unlike the Copy Op, this op has HostMemory constraint on its input or output.
79 debug_ops_spec: A list of debug op spec (op, url, gated_grpc) for attached debu
[all...] |
| /external/tensorflow/tensorflow/go/op/ |
| scope_test.go | 17 package op package
49 if got := c.Op.Name(); got != test.name {
122 if got, want := square.Op.Device(), "/device:GPU:0"; got != want {
125 if got, want := cube.Op.Device(), ""; got != want {
199 fmt.Println(c1.Op.Name(), c2.Op.Name())
|
