| /external/swiftshader/third_party/subzero/pydir/ |
| gen_test_arith_ll.py | 1 def mangle(op, op_type, signed):
17 base = 'test' + op.capitalize()
20 def arith(Native, Type, Op):
25 %result{{trunc}} = {{op}} {{type}} %a{{trunc}}, %b{{trunc}}
30 Signed = Op in {'sdiv', 'srem', 'ashr'}
31 Name = mangle(Op, Type, Signed)
33 if Type == 'i1' and (Op not in {'and', 'or', 'xor'}):
42 lines = x.format(native=Native, type=Type, op=Op, name=Name,
47 for op in ['add', 'sub', 'mul', 'sdiv', 'udiv', 'srem', 'urem', 'shl', 'lshr'
[all...] |
| /external/tensorflow/tensorflow/core/kernels/ |
| scan_ops_gpu.h | 90 template <typename T, typename Op>
94 Op op_;
96 __device__ BlockPrefixCallbackOp(T running_total, Op op)
97 : running_total_(running_total), op_(op) {}
122 template <typename T, typename Op>
125 (std::is_same<Op, Sum<T>>::value ||
126 std::is_same<Op, Eigen::internal::SumReducer<T>>::value);
129 template <typename T, typename Op>
132 (std::is_same<Op, Prod<T>>::value |
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreISelLowering.h | 87 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
136 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
137 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
142 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
143 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.cpp | 302 const auto Op = N->getOperand(i);
303 LLVM_DEBUG(dbgs() << "Analyzing operand: "; Op.dump(&DAG));
304 EVT OpVT = Op.getValueType();
513 SDValue Op = OrigOp;
515 AnalyzeNewValue(Op); // Op may morph.
517 if (Op.getNode()->getNodeId() == Processed)
522 NewOps.push_back(Op);
523 } else if (Op != OrigOp) {
526 NewOps.push_back(Op);
[all...] |
| /external/llvm/lib/Target/AVR/ |
| AVRISelLowering.h | 77 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
89 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
111 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
118 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
119 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/skia/src/gpu/effects/ |
| GrCoverageSetOpXP.h | 32 static const GrXPFactory* Get(SkRegion::Op regionOp, bool invertCoverage = false);
35 constexpr GrCoverageSetOpXPFactory(SkRegion::Op regionOp, bool invertCoverage);
53 SkRegion::Op fRegionOp;
|
| /external/skqp/src/gpu/effects/ |
| GrCoverageSetOpXP.h | 32 static const GrXPFactory* Get(SkRegion::Op regionOp, bool invertCoverage = false);
35 constexpr GrCoverageSetOpXPFactory(SkRegion::Op regionOp, bool invertCoverage);
51 SkRegion::Op fRegionOp;
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 79 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/DebugInfo/DWARF/ |
| DWARFExpression.h | 61 /// Description of the encoding of one expression Op.
63 DwarfVersion Version; ///< Dwarf version where the Op was introduced.
64 Encoding Op[2]; ///< Encoding for Op operands, or SizeNA.
69 Op[0] = Op1;
70 Op[1] = Op2;
76 uint8_t Opcode; ///< The Op Opcode, DW_OP_<something>.
101 Operation Op;
104 Op.Error =
106 !Op.extract(Expr->Data, Expr->Version, Expr->AddressSize, Offset)
[all...] |
| /external/eigen/unsupported/Eigen/src/Skyline/ |
| SkylineUtil.h | 27 #define EIGEN_SKYLINE_INHERIT_ASSIGNMENT_OPERATOR(Derived, Op) \
29 EIGEN_STRONG_INLINE Derived& operator Op(const Eigen::SkylineMatrixBase<OtherDerived>& other) \
31 return Base::operator Op(other.derived()); \
33 EIGEN_STRONG_INLINE Derived& operator Op(const Derived& other) \
35 return Base::operator Op(other); \
38 #define EIGEN_SKYLINE_INHERIT_SCALAR_ASSIGNMENT_OPERATOR(Derived, Op) \
40 EIGEN_STRONG_INLINE Derived& operator Op(const Other& scalar) \
42 return Base::operator Op(scalar); \
|
| /external/google-fruit/include/fruit/impl/injector/ |
| injector_accessor_for_tests.defn.h | 28 using Op = fruit::impl::meta::Eval<fruit::impl::meta::CheckNormalizedTypes(
30 (void)typename fruit::impl::meta::CheckIfError<Op>::type();
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 235 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
248 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
277 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
444 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
475 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
476 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
477 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
478 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/llvm/lib/CodeGen/ |
| MIRPrinter.cpp | 121 void printTargetFlags(const MachineOperand &Op);
122 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
125 void print(const MachineMemOperand &Op);
593 for (const auto *Op : MI.memoperands()) {
596 print(*Op);
690 void MIPrinter::printTargetFlags(const MachineOperand &Op) {
691 if (!Op.getTargetFlags())
694 Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
696 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
750 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI
[all...] |
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 58 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
342 auto Op = make_unique<SparcOperand>(k_Token);
343 Op->Tok.Data = Str.data();
344 Op->Tok.Length = Str.size();
345 Op->StartLoc = S;
346 Op->EndLoc = S;
347 return Op;
352 auto Op = make_unique<SparcOperand>(k_Register);
353 Op->Reg.RegNum = RegNum;
354 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 75 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
370 auto Op = make_unique<SparcOperand>(k_Token);
371 Op->Tok.Data = Str.data();
372 Op->Tok.Length = Str.size();
373 Op->StartLoc = S;
374 Op->EndLoc = S;
375 return Op;
380 auto Op = make_unique<SparcOperand>(k_Register);
381 Op->Reg.RegNum = RegNum;
382 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/ |
| PTXInstPrinter.cpp | 114 const MCOperand &Op = MI->getOperand(OpNo);
115 if (Op.isImm()) {
116 O << Op.getImm();
117 } else if (Op.isFPImm()) {
118 double Imm = Op.getFPImm();
129 assert(Op.isExpr() && "unknown operand kind in printOperand");
130 const MCExpr *Expr = Op.getExpr();
135 O << *Op.getExpr();
152 const MCOperand &Op = MI->getOperand(OpNo);
153 assert (Op.isImm() && "Rounding modes must be immediate values")
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.h | 48 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
74 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
75 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
77 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
80 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
81 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
82 SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
83 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
84 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
87 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/ |
| Uops.cpp | 108 const Operand &Op = Instr.Operands[OpIndex];
109 if (Op.IsDef)
156 const Operand &Op = Instr.Operands[Var->TiedOperands.front()];
157 assert(Op.Tracker);
161 for (const llvm::MCPhysReg Reg : Op.Tracker->sourceBits().set_bits()) {
171 for (const auto &Op : Instr.Operands) {
172 if (Op.Tracker && Op.IsExplicit && Op.IsDef) {
173 auto PossibleRegisters = Op.Tracker->sourceBits()
[all...] |
| /external/eigen/unsupported/Eigen/CXX11/src/Tensor/ |
| TensorScan.h | 17 template <typename Op, typename XprType>
18 struct traits<TensorScanOp<Op, XprType> >
29 template<typename Op, typename XprType>
30 struct eval<TensorScanOp<Op, XprType>, Eigen::Dense>
32 typedef const TensorScanOp<Op, XprType>& type;
35 template<typename Op, typename XprType>
36 struct nested<TensorScanOp<Op, XprType>, 1,
37 typename eval<TensorScanOp<Op, XprType> >::type>
39 typedef TensorScanOp<Op, XprType> type;
48 template <typename Op, typename XprType
[all...] |
| TensorReduction.h | 24 template<typename Op, typename Dims, typename XprType,template <class> class MakePointer_ >
25 struct traits<TensorReductionOp<Op, Dims, XprType, MakePointer_> >
43 template<typename Op, typename Dims, typename XprType, template <class> class MakePointer_>
44 struct eval<TensorReductionOp<Op, Dims, XprType, MakePointer_>, Eigen::Dense>
46 typedef const TensorReductionOp<Op, Dims, XprType, MakePointer_>& type;
49 template<typename Op, typename Dims, typename XprType, template <class> class MakePointer_>
50 struct nested<TensorReductionOp<Op, Dims, XprType, MakePointer_>, 1, typename eval<TensorReductionOp<Op, Dims, XprType, MakePointer_> >::type>
52 typedef TensorReductionOp<Op, Dims, XprType, MakePointer_> type;
129 template <int DimIndex, typename Self, typename Op>
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 40 // Add pseudo op to model memcpy for struct byval.
236 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
318 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
322 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
347 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
506 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
527 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
528 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
529 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
530 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG
[all...] |
| /external/llvm/include/llvm/Bitcode/ |
| BitstreamWriter.h | 261 /// record. This is a no-op, since the abbrev specifies the literal to use.
263 void EmitAbbreviatedLiteral(const BitCodeAbbrevOp &Op, uintty V) {
264 assert(Op.isLiteral() && "Not a literal");
267 assert(V == Op.getLiteralValue() &&
274 void EmitAbbreviatedField(const BitCodeAbbrevOp &Op, uintty V) {
275 assert(!Op.isLiteral() && "Literals should use EmitAbbreviatedLiteral!");
278 switch (Op.getEncoding()) {
281 if (Op.getEncodingData())
282 Emit((unsigned)V, (unsigned)Op.getEncodingData());
285 if (Op.getEncodingData()
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Bitcode/ |
| BitstreamWriter.h | 257 /// record. This is a no-op, since the abbrev specifies the literal to use.
259 void EmitAbbreviatedLiteral(const BitCodeAbbrevOp &Op, uintty V) {
260 assert(Op.isLiteral() && "Not a literal");
263 assert(V == Op.getLiteralValue() &&
270 void EmitAbbreviatedField(const BitCodeAbbrevOp &Op, uintty V) {
271 assert(!Op.isLiteral() && "Literals should use EmitAbbreviatedLiteral!");
274 switch (Op.getEncoding()) {
277 if (Op.getEncodingData())
278 Emit((unsigned)V, (unsigned)Op.getEncodingData());
281 if (Op.getEncodingData()
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 58 bool isSrcOp(X86Operand &Op);
62 bool isDstOp(X86Operand &Op);
373 bool X86ATTAsmParser::isSrcOp(X86Operand &Op) {
376 return (Op.isMem() &&
377 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
378 isa<MCConstantExpr>(Op.Mem.Disp) &&
379 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
380 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 153 // Compiler barrier only; generate a no-op.
292 // ATOMIC_LOAD_<op>.
295 // Operand 1: the second operand of <op>, in the high bits of an i32
432 void LowerAsmOperandForConstraint(SDValue Op,
481 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
509 void computeKnownBitsForTargetNode(const SDValue Op,
516 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
539 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
540 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
541 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
[all...] |
