| /external/llvm/lib/Transforms/IPO/ |
| GlobalOpt.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/ |
| JumpThreading.cpp | [all...] |
| RewriteStatepointsForGC.cpp | [all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceTargetLoweringX86Base.h | 43 /// lowerings (e.g., call, ret, and intrinsics.) Backends are expected to
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Pp2Dxe/ |
| Mvpp2Lib.c | 965 INT32 Ret = 0;
998 Ret = MVPP2_EINVAL;
1037 return Ret;
1114 INT32 TidAux, Tid, Ai, Ret = 0;
1133 Ret = Ai;
1156 Ret = MVPP2_ERANGE;
1186 return Ret;
3153 UINT32 ret; local
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 866 unsigned Ret = 4;
871 Ret = 3;
876 Ret = 2;
881 Ret = 1;
886 Ret = 0;
888 assert(Ret != 4 && "Invalid CR bit register");
889 return Ret;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Instrumentation/ |
| AddressSanitizer.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/MC/ |
| ELFObjectWriter.cpp | [all...] |
| /external/v8/src/mips/ |
| macro-assembler-mips.h | 242 // Jump, Call, and Ret pseudo instructions implementing inter-working.
266 void Ret(COND_ARGS);
267 inline void Ret(BranchDelaySlot bd, Condition cond = al,
269 Ret(cond, rs, rt, bd);
[all...] |
| /external/v8/src/mips64/ |
| macro-assembler-mips64.h | 262 // Jump, Call, and Ret pseudo instructions implementing inter-working.
283 void Ret(COND_ARGS);
284 inline void Ret(BranchDelaySlot bd, Condition cond = al,
286 Ret(cond, rs, rt, bd);
[all...] |
| /external/v8/src/regexp/arm64/ |
| regexp-macro-assembler-arm64.cc | [all...] |
| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Library/GenericBdsLib/ |
| BdsBoot.c | 457 BOOLEAN Ret;
471 Ret = TRUE;
474 Ret = FALSE;
477 return Ret;
[all...] |
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/ |
| BdsBoot.c | 459 BOOLEAN Ret;
473 Ret = TRUE;
476 Ret = FALSE;
479 return Ret;
[all...] |
| /external/llvm/lib/Analysis/ |
| ObjCARCInstKind.cpp | 238 // operands of interest. And ret is never followed by a release, so it's
265 case Instruction::Ret:
|
| /external/llvm/lib/IR/ |
| Instruction.cpp | 261 case Ret: return "ret";
|
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | [all...] |
| MipsISelLowering.h | 68 Ret,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 486 // Replace CATCHRET with the appropriate RET.
493 // Replace CATCHRET with the appropriate RET.
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86FastISel.cpp | 688 /// X86SelectRet - Select and emit code to implement ret instructions.
690 const ReturnInst *Ret = cast<ReturnInst>(I);
719 if (Ret->getNumOperands() > 0) {
730 const Value *RV = Ret->getOperand(0);
791 // Now emit the RET.
792 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| ObjCARCInstKind.cpp | 244 // operands of interest. And ret is never followed by a release, so it's
271 case Instruction::Ret:
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | [all...] |
| MipsISelLowering.h | 119 Ret,
|
