| /external/boringssl/src/ssl/test/runner/poly1305/ |
| sum_vmsl_s390x.s | 427 SUB $81, R3
462 SUB $16, R3
475 SUB $64, R3
590 SUB $49, R3
620 SUB $16, R3
663 SUB $33, R3
715 SUB $16, R3
770 SUB $17, R3
801 SUB $16, R3, R3
845 SUB $1, R
[all...] |
| sum_arm.s | 203 SUB $16, R12, R12
273 SUB R2, R6, R6
382 SUB $1, R12
|
| sum_s390x.s | 248 SUB $32, R3
309 SUB $17, R3
346 SUB $1, R3
|
| /external/libhevc/common/arm/ |
| ihevc_resi_trans_32x32_a9q.s | 108 SUB SP,SP,#32
159 SUB R4, R4, #16
160 SUB R5, R5, #16
303 SUB R2,R2,R10,LSL #2
370 SUB R2,R2,R10,LSL #2
371 SUB R2,R2,R7,LSL #2
442 SUB R12, R12, #16
509 SUB R2,R2,R7, LSL #3
511 SUB R2,R2,R7, LSL #1
789 SUB R2,R2,R7,LSL #
[all...] |
| ihevc_resi_trans.s | 630 SUB r2,r2,#176 @ r2 now points to the second row
[all...] |
| ihevc_sao_band_offset_luma.s | 88 SUB r10,r10,#1 @wd-1
108 SUB r12,r8,#1 @ht-1
|
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| Rops.java | 227 new Rop(RegOps.SUB, Type.INT, StdTypeList.INT_INT, "sub-int");
231 new Rop(RegOps.SUB, Type.LONG, StdTypeList.LONG_LONG, "sub-long");
235 new Rop(RegOps.SUB, Type.FLOAT, StdTypeList.FLOAT_FLOAT, "sub-float");
239 new Rop(RegOps.SUB, Type.DOUBLE, StdTypeList.DOUBLE_DOUBLE,
240 Rop.BRANCH_NONE, "sub-double");
388 new Rop(RegOps.SUB, Type.INT, StdTypeList.INT, "sub-const-int")
[all...] |
| /dalvik/dx/src/com/android/dx/rop/code/ |
| Rops.java | 228 new Rop(RegOps.SUB, Type.INT, StdTypeList.INT_INT, "sub-int");
232 new Rop(RegOps.SUB, Type.LONG, StdTypeList.LONG_LONG, "sub-long");
236 new Rop(RegOps.SUB, Type.FLOAT, StdTypeList.FLOAT_FLOAT, "sub-float");
240 new Rop(RegOps.SUB, Type.DOUBLE, StdTypeList.DOUBLE_DOUBLE,
241 Rop.BRANCH_NONE, "sub-double");
389 new Rop(RegOps.SUB, Type.INT, StdTypeList.INT, "sub-const-int")
[all...] |
| /external/v8/src/compiler/ |
| machine-operator.cc | 421 V(Sub) \
[all...] |
| /external/libxaac/decoder/armv8/ |
| ixheaacd_overlap_add1.s | 51 SUB X11, X10, #1
54 SUB X10, X10, #12
57 SUB X8, X8, #14
70 SUB X11, X5, #1
147 SUB W5, W5, #8
|
| ixheaacd_post_twiddle_overlap.s | 66 SUB x6, x6, #4
75 sub x20, x5, #15
79 SUB x5, x5, #16
121 SUB x8, x12, x11
162 SUB x9, x11, #16
180 SUB x9, x11, #31
195 SUB x9, x11, #31
288 SUB x0, x5, x10
301 SUB x1, x1, #40
310 SUB x3, x3, #
[all...] |
| /external/one-true-awk/ |
| awkgram.y | 56 %token <i> SUB GSUB IF INDEX LSUBSTR MATCHFCN NEXT NEXTFILE
84 %left PRINT PRINTF RETURN SPLIT SPRINTF STRING SUB SUBSTR
348 SUB | GSUB
|
| lex.c | 42 int sub; member in struct:Keyword
84 { "sub", SUB, SUB },
467 yylval.i = kp->sub;
470 if (kp->sub == FSYSTEM && safe)
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| AVRISelDAGToDAG.cpp | 80 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
89 if (N.getOpcode() == ISD::SUB) {
240 if (Op->getOpcode() == ISD::ADD || Op->getOpcode() == ISD::SUB) {
|
| /external/tensorflow/tensorflow/core/kernels/ |
| scatter_functor.h | 41 enum class UpdateOp { ASSIGN, ADD, SUB, MUL, DIV, MIN, MAX };
70 struct Assign<scatter_op::UpdateOp::SUB> {
147 struct AssignSYCL<scatter_op::UpdateOp::SUB> {
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| Syn_filt_32_opt.s | 206 SUB r14, r14, r6
213 SUB r9, r14, r7, LSL #12 @ sig_lo[i] = L_tmp - (sig_hi[i] << 12)
|
| /external/deqp/framework/qphelper/ |
| qpXmlWriter.c | 89 case 26: repl = "<SUB>"; break;
|
| /external/libavc/encoder/arm/ |
| ih264e_fmt_conv.s | 81 sub r7, r7, r5 @// Source increment
82 sub r8, r8, r5 @// Destination increment
91 sub r6, r6, #16
102 sub r0, r0, r6
103 sub r3, r3, r6
127 sub r7, r7, r5, lsr #1 @// Source increment
129 sub r8, r8, r5 @// Destination increment
145 sub r6, r6, #8
156 sub r1, r1, r6
157 sub r2, r2, r
[all...] |
| /external/libxaac/decoder/armv7/ |
| ixheaacd_inv_dit_fft_8pt.s | 39 SUB sp, sp, #0x14
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
212 /// results. The first result is the normal add or sub result, the second
218 /// the add or sub, and the third is the input carry flag. These nodes
219 /// produce two results; the normal result of the add or sub, and the output
221 /// to them to be chained together for add and sub of arbitrarily large
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUTargetTransformInfo.cpp | 143 case ISD::SUB:
|
| /external/llvm/lib/Target/Lanai/ |
| LanaiRegisterInfo.cpp | 213 // LPAC::SUB with the already negated offset.
216 MI.getOperand(3).setImm(LPAC::SUB);
|
| /external/mesa3d/src/gallium/drivers/vc4/ |
| vc4_qpu.h | 203 A_ALU2(SUB)
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| hsw_sol.c | 108 OUT_BATCH(MI_MATH_ALU0(SUB));
|
