| /external/mesa3d/src/mesa/program/ |
| program_lexer.l | 223 SUB{sat} { return_opcode( 1, BIN_OP, SUB, 3); }
|
| /external/sonivox/arm-wt-22k/lib_src/ |
| ARM-E_interpolate_loop_gnu.s | 94 SUB tmp1, tmp1, tmp0 @ tmp1 = x1 - x0
|
| ARM-E_interpolate_noloop_gnu.s | 86 SUB tmp1, tmp1, tmp0 @ tmp1 = x1 - x0
|
| /external/swiftshader/src/Shader/ |
| PixelPipeline.hpp | 76 void SUB(Vector4s &dst, Vector4s &src0, Vector4s &src1);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 201 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
218 /// results. The first result is the normal add or sub result, the second
227 /// the add or sub, and the third is the input carry flag. These nodes
228 /// produce two results; the normal result of the add or sub, and the output
230 /// to them to be chained together for add and sub of arbitrarily large
236 /// rhs to the add or sub, and the third is a boolean indicating if there
238 /// result of the add or sub, and the output carry so they can be chained
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| LanaiRegisterInfo.cpp | 213 // LPAC::SUB with the already negated offset.
216 MI.getOperand(3).setImm(LPAC::SUB);
|
| LanaiISelLowering.cpp | 143 setTargetDAGCombine(ISD::SUB);
[all...] |
| LanaiMemAluCombiner.cpp | 209 return LPAC::SUB;
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| /external/tensorflow/tensorflow/core/kernels/ |
| scatter_functor_gpu.cu.h | 48 struct ScatterOpKernelBody<T, scatter_op::UpdateOp::SUB> {
|
| scatter_nd_op.cc | 354 scatter_nd_op::UpdateOp::SUB); \
358 type, dev, "ResourceScatterNdSub", scatter_nd_op::UpdateOp::SUB);
410 scatter_nd_op::UpdateOp::SUB>)
429 // Register TensorScatterUpdate/Add/Sub for all number types.
[all...] |
| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| tgsi_opcode_tmp.h | 10 * distribute, sub license, and/or sell copies of the Software, and to
76 OP12(SUB)
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| Dot_p_neon.s | 117 SUB r10, r10, #1 @ sft = norm_l(L_sum)
|
| /external/libxaac/decoder/armv7/ |
| ixheaacd_post_twiddle_overlap.s | 38 SUB R6, R6, #4
49 SUB R5, R5, #16
68 SUB R8, R12, R11
165 SUB R0, R5, R10
178 SUB R1, R1, #40
187 SUB R3, R3, #4
189 SUB R3, R3, #2
|
| ixheaacd_sbr_qmfanal32_winadds.s | 144 SUB R5, R5, #1
|
| /external/pdfium/third_party/libopenjpeg20/ |
| dwt.c | 611 #define SUB(x,y) _mm256_sub_epi32((x),(y))
621 #define SUB(x,y) _mm_sub_epi32((x),(y))
685 s0n_0 = SUB(s1n_0, SAR(ADD3(d1n_0, d1n_0, two), 2));
686 s0n_1 = SUB(s1n_1, SAR(ADD3(d1n_1, d1n_1, two), 2));
700 s0n_0 = SUB(s1n_0, SAR(ADD3(d1c_0, d1n_0, two), 2));
701 s0n_1 = SUB(s1n_1, SAR(ADD3(d1c_1, d1n_1, two), 2));
720 tmp_len_minus_1 = SUB(s1n_0, SAR(ADD3(d1n_0, d1n_0, two), 2));
728 tmp_len_minus_1 = SUB(s1n_1, SAR(ADD3(d1n_1, d1n_1, two), 2));
782 dc_0 = SUB(LOADU(in_odd + 0),
788 dc_1 = SUB(LOADU(in_odd + VREG_INT_COUNT)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| TargetLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 447 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
469 if (N.getOpcode() == ISD::SUB)
502 AddSub = ARM_AM::sub;
517 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
531 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
557 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
602 AddSub = ARM_AM::sub;
617 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
637 if (N.getOpcode() != ISD::SUB) {
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| /dalvik/dx/src/com/android/dx/ssa/ |
| SCCP.java | 408 case RegOps.SUB:
409 // 1 source for reverse sub, 2 sources for regular sub
509 case RegOps.SUB:
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 81 setOperationAction(ISD::SUB, T, Legal);
150 setOperationAction(ISD::SUB, T, Legal);
645 SDValue SubV = DAG.getNode(ISD::SUB, dl, MVT::i32,
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiMemAluCombiner.cpp | 209 return LPAC::SUB;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| RISCVFrameLowering.cpp | 74 Opc = RISCV::SUB;
|
| /external/libhevc/common/arm/ |
| ihevc_sao_band_offset_chroma.s | 98 SUB r12,r12,#2 @wd-2
118 SUB r4,r10,#1 @ht-1
339 SUB r9,r9,#16 @Decrement the width loop by 16
|
| /external/libhevc/decoder/arm64/ |
| ihevcd_fmt_conv_420sp_to_rgba8888.s | 96 stp d8,d15,[sp,#-16]! // Storing d15 using { sub sp,sp,#8; str d15,[sp] } is giving bus error.
149 SUB x10,x6,x3 //// luma offset
150 SUB x11,x7,x3
152 //SUB x12,x8,x3, LSR #1 @// v offset
153 SUB x14,x9,x3 //// rgb offset in pixels
|
