| /device/linaro/bootloader/edk2/Omap35xxPkg/Flash/ |
| Flash.h | 77 #define NAND_FAILURE BIT0
|
| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/ |
| VirtioGpu.h | 79 #define VIRTIO_GPU_FLAG_FENCE BIT0
|
| /device/linaro/bootloader/edk2/OvmfPkg/Include/Library/ |
| QemuFwCfgLib.h | 36 #define FW_CFG_DMA_CTL_ERROR BIT0
|
| /device/linaro/bootloader/edk2/OvmfPkg/Library/PciHostBridgeLib/ |
| XenSupport.c | 94 if ((Value & BIT0) == BIT0) {
282 if (Value == BIT0) {
317 if (Value == BIT0) {
|
| /device/linaro/bootloader/edk2/SecurityPkg/Include/Library/ |
| TpmCommLib.h | 161 #define TIS_PC_ACC_ESTABLISH BIT0
|
| /device/linaro/bootloader/edk2/ShellPkg/Library/UefiShellDriver1CommandsLib/ |
| UefiShellDriver1CommandsLib.c | 54 if ((PcdGet8(PcdShellProfileMask) & BIT0) == 0) {
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/ResetSystemLib/ |
| ResetSystemLib.c | 117 PchPmioBase = (UINT16) (PciRead16 (PCI_LIB_ADDRESS(0, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ACPI_BASE)) & ~BIT0);
|
| /device/linaro/bootloader/edk2/ArmPkg/Include/Chipset/ |
| ArmV7Mmu.h | 25 #define TTBR_INNER_CACHEABLE BIT0
29 #define TTBR_RGN_INNER_WRITE_THROUGH BIT0
30 #define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
|
| /device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/ |
| Acpi50.h | 313 #define EFI_ACPI_5_0_LEGACY_DEVICES BIT0
324 #define EFI_ACPI_5_0_WBINVD BIT0
373 #define EFI_ACPI_5_0_S4BIOS_F BIT0
380 #define EFI_ACPI_5_0_OSPM_64BIT_WAKE_F BIT0
411 #define EFI_ACPI_5_0_PCAT_COMPAT BIT0
450 #define EFI_ACPI_5_0_LOCAL_APIC_ENABLED BIT0
577 #define EFI_ACPI_5_0_CPEI_PROCESSOR_OVERRIDE BIT0
622 #define EFI_ACPI_5_0_GIC_ENABLED BIT0
[all...] |
| Acpi40.h | 188 #define EFI_ACPI_4_0_LEGACY_DEVICES BIT0
198 #define EFI_ACPI_4_0_WBINVD BIT0
245 #define EFI_ACPI_4_0_S4BIOS_F BIT0
252 #define EFI_ACPI_4_0_OSPM_64BIT_WAKE__F BIT0
283 #define EFI_ACPI_4_0_PCAT_COMPAT BIT0
320 #define EFI_ACPI_4_0_LOCAL_APIC_ENABLED BIT0
447 #define EFI_ACPI_4_0_CPEI_PROCESSOR_OVERRIDE BIT0
[all...] |
| Pal.h | 32 #define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0
639 #define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/ |
| UfsPassThru.c | 204 if ((Private->Luns.BitMask & (BIT0 << Index)) == 0) {
279 if ((Private->Luns.BitMask & (BIT0 << Index)) != 0) {
309 if ((Private->Luns.BitMask & (BIT0 << Index)) == 0) {
318 if ((Private->Luns.BitMask & (BIT0 << Next)) != 0) {
408 if ((Private->Luns.BitMask & (BIT0 << Index)) == 0) {
499 if ((Private->Luns.BitMask & (BIT0 << Index)) == 0) {
[all...] |
| UfsPassThruHci.c | 358 Flags = BIT0 | BIT6;
360 Flags = BIT0 | BIT5;
362 Flags = BIT0;
403 if ((BufferSize & (BIT0 | BIT1)) != 0) {
404 BufferSize &= ~(BIT0 | BIT1);
412 ASSERT (((UINTN)Buffer & (BIT0 | BIT1)) == 0);
763 if ((Data & (BIT0 << Index)) == 0) {
828 Status = UfsMmioWrite32 (Private, UFS_HC_UTRLDBR_OFFSET, BIT0 << Slot);
857 if ((Data & (BIT0 << Slot)) != 0) {
863 Status = UfsMmioWrite32 (Private, UFS_HC_UTRLCLR_OFFSET, Data & ~(BIT0 << Slot));
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/SdMmc/XenonDxe/ |
| SdMmcPciHci.c | 656 BIT0 | BIT1,
772 ClockCtrl |= BIT0;
829 PowerCtrl &= (UINT8)~BIT0;
838 PowerCtrl |= BIT0;
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ |
| SdMmcPciHci.c | 656 BIT0 | BIT1,
772 ClockCtrl |= BIT0;
829 PowerCtrl &= (UINT8)~BIT0;
838 PowerCtrl |= BIT0;
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ufs/UfsBlockIoPei/ |
| UfsHci.c | 287 Flags = BIT0 | BIT6;
289 Flags = BIT0 | BIT5;
291 Flags = BIT0;
332 if ((BufferSize & (BIT0 | BIT1)) != 0) {
333 BufferSize &= ~(BIT0 | BIT1);
341 ASSERT (((UINTN)Buffer & (BIT0 | BIT1)) == 0);
728 MmioWrite32 (Address, BIT0 << Slot);
752 if ((Data & (BIT0 << Slot)) != 0) {
755 MmioWrite32 (Address, (Data & ~(BIT0 << Slot)));
847 Status = UfsWaitMemSet (Address, BIT0 << Slot, 0, Packet.Timeout);
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/ |
| EmmcHci.c | 484 BIT0 | BIT1,
602 ClockCtrl |= BIT0;
655 PowerCtrl &= (UINT8)~BIT0;
664 PowerCtrl |= BIT0;
899 HostCtrl1 = BIT0;
902 HostCtrl1 = (UINT8)~BIT0;
944 if ((Data & (BIT0 | BIT1)) != 0) {
1114 PresentState = BIT0 | BIT1;
1120 PresentState = BIT0;
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Include/Library/ |
| HwMemInitLib.h | 626 #define ETR BIT0 // Bit location for Extended Temp Range
749 #define SPD_MAC_MASK BIT0 | BIT1 | BIT2 // Mask for Maximum Active Count field
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Usb/DwUsbDxe/ |
| DwUsbDxe.h | 54 #define DW_DC_INTERRUPT_BRESET BIT0
89 #define DW_SW_RESET_ALL BIT0
100 #define DW_OTG_CTRL_DP_PULLUP BIT0
230 #define GINTSTS_CURMODE_HOST BIT0
403 #define DXEPMSK_XFERCOMPLMSK BIT0
495 #define DXEPINT_XFERCOMPL BIT0
|
| /device/linaro/bootloader/edk2/CorebootPayloadPkg/Library/PciHostBridgeLib/ |
| PciHostBridgeSupport.c | 210 if ((Value & BIT0) == BIT0) {
408 if (Value == BIT0) {
443 if (Value == BIT0) {
|
| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/ |
| InternalIsaIo.h | 23 #define PCD_ISA_BUS_SUPPORT_DMA BIT0
|
| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/ |
| IsaIo.h | 23 #define PCD_ISA_BUS_SUPPORT_DMA BIT0
|
| /device/linaro/bootloader/edk2/IntelSiliconPkg/Include/IndustryStandard/ |
| IgdOpRegion.h | 23 #define IGD_OPREGION_HEADER_MBOX1 BIT0
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Core/DxeIplPeim/X64/ |
| VirtualMemory.h | 148 #define IA32_PG_P BIT0
|
| /device/linaro/bootloader/edk2/OvmfPkg/Library/PlatformBootManagerLib/ |
| BdsPlatform.h | 158 #define CONSOLE_OUT BIT0
|
