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Searched
refs:BIT0
(Results
26 - 50
of
257
) sorted by null
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/device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/
DmaRemappingReportingTable.h
33
#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP
BIT0
50
#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL
BIT0
65
#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS
BIT0
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/
TPS65950.h
40
#define CARD_DETECT_ENABLE (BIT2 |
BIT0
) // GPIO ON + GPIO CD1 enabled
44
#define CARD_DETECT_BIT
BIT0
48
#define LEDAON
BIT0
/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
Virtio095Net.h
44
#define VIRTIO_NET_F_CSUM
BIT0
// host to checksum outgoing packets
80
#define VIRTIO_NET_HDR_F_NEEDS_CSUM
BIT0
94
#define VIRTIO_NET_S_LINK_UP
BIT0
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
QuarkNcSocId.h
134
#define B_DFUSESTAT_ECC_DIS (
BIT0
) // Disable ECC.
146
#define OPTIONS_1_DMA_DISABLE (
BIT0
)
226
#define CPU0_NON_SMM
BIT0
240
#define SMM_LOCKED (
BIT0
) // SMM Locked
245
#define HMBOUND_LOCK
BIT0
284
#define B_STPDDRCFG_FORCE_RECOVERY
BIT0
315
#define B_TSCGF3_CONFIG_ITSRST
BIT0
329
#define B_CFG_STICKY_RW_SMM_VIOLATION
BIT0
398
#define B_QNC_SMBUS_BYTE_DONE_STS (
BIT0
) // Completion Status
446
#define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+
BIT0
)
[
all
...]
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/
Lan91xDxeHw.h
75
#define TCR_TXENA
BIT0
90
#define EPHSR_TX_SUC
BIT0
105
#define RCR_RX_ABORT
BIT0
137
#define CTR_STORE
BIT0
150
#define MMUCR_BUSY
BIT0
183
#define IST_RCV
BIT0
192
#define MGMT_MDO
BIT0
203
#define RX_MULTICAST
BIT0
255
#define PHYSTS_EXT_CAP
BIT0
// Extended Capabilities Register capability
269
#define PHYANA_CSMA
BIT0
// Advertise CSMA capability
[
all
...]
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530MMCHS.h
27
#define RESETDONE_MASK
BIT0
28
#define RESETDONE
BIT0
34
#define OD
BIT0
57
#define DE_ENABLE
BIT0
79
#define CMDI_MASK
BIT0
81
#define CMDI_NOT_ALLOWED
BIT0
97
#define ICE
BIT0
112
#define CC
BIT0
123
#define CC_EN
BIT0
138
#define CC_SIGEN
BIT0
[
all
...]
Omap3530Gpio.h
61
#define GPIO_SYSCONFIG_AUTOIDLE_MASK
BIT0
63
#define GPIO_SYSCONFIG_AUTOIDLE_ON
BIT0
65
#define GPIO_SYSSTATUS_RESETDONE_MASK
BIT0
67
#define GPIO_SYSSTATUS_RESETDONE_COMPLETE
BIT0
87
#define GPIO_CTRL_DISABLEMODULE_MASK
BIT0
89
#define GPIO_CTRL_DISABLEMODULE_DISABLE
BIT0
Omap3530Gpmc.h
29
#define TIMEOUTENABLE
BIT0
57
#define OEONTIME
BIT0
84
#define ECCENABLE
BIT0
90
#define ECCPOINTER_REG1
BIT0
Omap3530Prcm.h
79
#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK
BIT0
81
#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE
BIT0
83
#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK
BIT0
85
#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE
BIT0
Omap3530Usb.h
43
#define UHH_SYSSTATUS_RESETDONE (
BIT0
| BIT1 | BIT2)
Omap3530Interrupt.h
45
#define INTCPS_ILR_FIQ
BIT0
47
#define INTCPS_CONTROL_NEWIRQAGR
BIT0
/device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/
SataRegisters.h
26
#define EFI_AHCI_GHC_RESET
BIT0
90
#define EFI_AHCI_PORT_IS_DHRS
BIT0
116
#define EFI_AHCI_PORT_CMD_ST
BIT0
136
#define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 |
BIT0
)
139
#define EFI_AHCI_PORT_TFD_ERR
BIT0
158
#define EFI_AHCI_PORT_SERR_RDIE
BIT0
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
UhciReg.h
49
#define USBPORTSC_CCS
BIT0
// Current Connect Status
70
#define USBCMD_RS
BIT0
// Run/Stop
82
#define USBSTS_USBINT
BIT0
// Interrupt due to IOC
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsSpi.h
57
#define B_PCH_SPI_HSFS_FDONE
BIT0
// Flash Cycle Done
83
#define B_PCH_SPI_OPTYPE0_MASK (BIT1 |
BIT0
) // Opcode Type 0 Mask
115
#define B_PCH_SPI_BCR_BIOSWE
BIT0
// Write Protect Disable (WPD)
/device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
SP804Timer.h
33
#define SP804_TIMER_CTRL_ONESHOT
BIT0
/device/linaro/bootloader/edk2/DuetPkg/PciBusNoEnumerationDxe/
PciPowerManagement.c
86
PowerManagementCSR &= ~(BIT8 | BIT1 |
BIT0
);
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/PciBusDxe/
PciPowerManagement.c
73
PowerManagementCSR &= ~(BIT8 | BIT1 |
BIT0
);
/device/linaro/bootloader/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/
SmmStmSupport.c
23
#define IA32_PG_P
BIT0
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/
I2CRegs.h
33
#define B_MASTER_MODE
BIT0
65
#define I2C_INTR_RX_UNDER
BIT0
125
#define I2C_INTR_RX_UNDER
BIT0
129
#define B_PCH_LPIO_I2C_MEM_RESETS_APB
BIT0
// APB Domain Reset
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/VlvPlatformInitDxe/
VlvPlatformInit.h
68
#define LockBit
BIT0
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/
IdeMode.h
64
#define BMIC_START
BIT0
118
#define IDE_PRIMARY_OPERATING_MODE
BIT0
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibPei/
I2CLibPei.h
32
#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC0
BIT0
// LPSS DMA Disable
52
#define B_PCH_LPSS_I2C_BAR_MS
BIT0
// Message Space
59
#define B_PCH_LPSS_I2C_BAR1_MS
BIT0
// Message Space
68
#define B_PCH_LPIO_I2C_MEM_RESETS_APB
BIT0
// APB Domain Reset
86
#define B_MASTER_MODE
BIT0
118
#define I2C_INTR_RX_UNDER
BIT0
182
#define I2C_INTR_RX_UNDER
BIT0
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/
Isp1761UsbDxe.h
42
#define ISP1761_DC_INTERRUPT_BRESET
BIT0
89
#define ISP1761_SW_RESET_ALL
BIT0
100
#define ISP1761_OTG_CTRL_DP_PULLUP
BIT0
/device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/
IdeData.h
113
#define IDE_PRIMARY_OPERATING_MODE
BIT0
123
#define BMIC_START
BIT0
309
#define TIME0
BIT0
/device/linaro/bootloader/edk2/MdeModulePkg/Include/Library/
LockBoxLib.h
67
#define LOCK_BOX_ATTRIBUTE_RESTORE_IN_PLACE
BIT0
Completed in 1653 milliseconds
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