/device/linaro/bootloader/OpenPlatformPkg/Drivers/SdMmc/XenonDxe/ |
EmmcDevice.c | 545 if ((HostCtrl2 & (BIT6 | BIT7)) == 0) {
549 if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {
558 HostCtrl2 = (UINT8)~(BIT6 | BIT7);
633 if ((DevStatus & BIT7) != 0) {
701 if ((DevStatus & BIT7) != 0) {
[all...] |
SdDevice.c | 791 if ((HostCtrl2 & (BIT6 | BIT7)) == 0) {
794 if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {
803 HostCtrl2 = (UINT8)~(BIT6 | BIT7);
[all...] |
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ |
EmmcDevice.c | 545 if ((HostCtrl2 & (BIT6 | BIT7)) == 0) {
549 if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {
558 HostCtrl2 = (UINT8)~(BIT6 | BIT7);
633 if ((DevStatus & BIT7) != 0) {
701 if ((DevStatus & BIT7) != 0) {
[all...] |
SdDevice.c | 791 if ((HostCtrl2 & (BIT6 | BIT7)) == 0) {
794 if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {
803 HostCtrl2 = (UINT8)~(BIT6 | BIT7);
[all...] |
/device/linaro/bootloader/edk2/OptionRomPkg/AtapiPassThruDxe/ |
AtapiPassThru.h | 209 #define BBK_ERR BIT7 ///< Bad block detected
221 #define SENSE_KEY_ERR (BIT7 | BIT6 | BIT5 | BIT4)
243 #define BSY BIT7 ///< Controller Busy
[all...] |
/device/linaro/bootloader/edk2/ArmPkg/Include/Chipset/ |
AArch64.h | 82 #define SPSR_I BIT7
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/device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/ |
BaseTypes.h | 228 #define BIT7 0x00000080
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/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/ |
UsbMassBoot.h | 221 #define USB_BOOT_REMOVABLE(RmbByte) (((RmbByte) & BIT7) != 0)
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/device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/ |
Pci22.h | 587 #define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080
601 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080
610 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080
620 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080
|
PeImage.h | 103 #define EFI_IMAGE_FILE_BYTES_REVERSED_LO BIT7 ///< 0x0080 Bytes of machine word are reversed.
306 #define EFI_IMAGE_SCN_CNT_UNINITIALIZED_DATA BIT7 ///< 0x00000080
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/device/linaro/bootloader/edk2/OvmfPkg/Library/QemuFwCfgLib/ |
QemuFwCfgLib.c | 398 return (BOOLEAN) (SystemStates[3] & BIT7);
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/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/NorFlashDxe/ |
NorFlashDxe.h | 56 #define P30_SR_BIT_WRITE (BIT7 << 16 | BIT7)
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/device/linaro/bootloader/edk2/OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772/ |
Ax88772.h | 60 #define USB_IS_IN_ENDPOINT(EndPointAddr) (((EndPointAddr) & BIT7) != 0) ///< Return TRUE/FALSE for IN direction
61 #define USB_IS_OUT_ENDPOINT(EndPointAddr) (((EndPointAddr) & BIT7) == 0) ///< Return TRUE/FALSE for OUT direction
[all...] |
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/ |
CEATA.c | 304 if (((Data & BIT7) == 0) && ((Data & BIT6) == BIT6)) {
345 if (((Data & BIT7) == 0) && ((Data & BIT3) == 0)) {
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/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/ |
EmmcHci.c | 430 if ((Data & (BIT6 | BIT7)) != 0) {
432 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
434 Data &= BIT6 | BIT7;
[all...] |
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
meminit.c | 581 isbM32m(DDRPHY, (B0RXIOBUFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), ((0x0<<7)|(0x0<<0)), (BIT7|BIT0)); // AFE Bypass, RCVEN DIFFAMP
582 isbM32m(DDRPHY, (B1RXIOBUFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), ((0x0<<7)|(0x0<<0)), (BIT7|BIT0)); // AFE Bypass, RCVEN DIFFAMP
587 isbM32m(DDRPHY, (B0VREFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), ((0x03<<2)|(0x0<<1)|(0x0<<0)), ((BIT7|BIT6|BIT5|BIT4|BIT3|BIT2)|BIT1|BIT0)); // Internal Vref Code, Enable#, Ext_or_Int (1=Ext)
588 isbM32m(DDRPHY, (B1VREFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), ((0x03<<2)|(0x0<<1)|(0x0<<0)), ((BIT7|BIT6|BIT5|BIT4|BIT3|BIT2)|BIT1|BIT0)); // Internal Vref Code, Enable#, Ext_or_Int (1=Ext)
599 isbM32m(DDRPHY, (CMDRCOMPODT + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x03<<5)|(0x03<<0)), ((BIT9|BIT8|BIT7|BIT6|BIT5)|(BIT4|BIT3|BIT2|BIT1|BIT0)));
602 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
603 isbM32m(DDRPHY, (CMDPMDLYREG3 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT_for_PM_MSG_gt0, MDLL Turn On
604 isbM32m(DDRPHY, (CMDPMDLYREG2 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // MPLL Divider Reset Delays
605 isbM32m(DDRPHY, (CMDPMDLYREG1 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn Off Delays: VREG, Staggered MDLL, MDLL, PI
606 isbM32m(DDRPHY, (CMDPMDLYREG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: MPLL, Staggered MDLL, PI, IOBUFACT [all...] |
/device/linaro/bootloader/edk2/OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772b/ |
Ax88772.h | 67 #define USB_IS_IN_ENDPOINT(EndPointAddr) (((EndPointAddr) & BIT7) != 0) ///< Return TRUE/FALSE for IN direction
68 #define USB_IS_OUT_ENDPOINT(EndPointAddr) (((EndPointAddr) & BIT7) == 0) ///< Return TRUE/FALSE for OUT direction
[all...] |
/device/linaro/bootloader/edk2/OvmfPkg/AcpiPlatformDxe/ |
Qemu.c | 378 if (SystemStates[3] & BIT7) {
388 if (SystemStates[4] & BIT7) {
|
/device/linaro/bootloader/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/ |
SmiEntry.S | 120 testl $BIT7, %edx # Check for MCE capabilities
259 testl $BIT7, %edx # Check for MCE capabilities
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/bionic/libc/kernel/uapi/linux/ |
synclink.h | 30 #define BIT7 0x0080
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/device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960UsbDxe/ |
HiKey960UsbDxe.c | 157 HiKey960UsbPhyCrWrite (DWC3_PHY_RX_OVRD_IN_HI, BIT11 | BIT9 | BIT8 |BIT7);
|
/device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/ |
Ps2Keyboard.h | 201 #define KEYBOARD_STATUS_REGISTER_PARITY BIT7 ///< 0 - Odd parity; 1 - Even parity
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/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/ |
Ps2Keyboard.h | 202 #define KEYBOARD_STATUS_REGISTER_PARITY BIT7 ///< 0 - Odd parity; 1 - Even parity
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/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
XhciReg.h | 170 #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
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/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
XhciReg.h | 85 #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
|