| /external/python/cpython3/Modules/ |
| sha1module.c | 105 #define F0(x,y,z) (z ^ (x & (y ^ z)))
133 #define FF_0(a,b,c,d,e,i) e = (ROLc(a, 5) + F0(b,c,d) + e + W[i] + 0x5a827999UL); b = ROLc(b, 30);
|
| /external/tensorflow/tensorflow/lite/kernels/internal/optimized/ |
| optimized_ops.h | [all...] |
| /art/compiler/jni/quick/mips/ |
| calling_convention_mips.cc | 88 return MipsManagedRegister::FromFRegister(F0);
|
| /art/runtime/arch/mips/ |
| callee_save_frame_mips.h | 75 (1 << art::mips::F0) | (1 << art::mips::F1) | (1 << art::mips::F2) | (1 << art::mips::F3) |
|
| /art/runtime/arch/mips64/ |
| callee_save_frame_mips64.h | 63 (1 << art::mips64::F0) | (1 << art::mips64::F1) | (1 << art::mips64::F2) |
|
| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 851 EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
854 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
857 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
860 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 908 EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
911 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
914 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
917 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 76 MAP(F0, 112) \
|
| /external/webp/src/dsp/ |
| lossless_enc_sse2.c | 108 const __m128i F0 = _mm_srli_epi32(C0, 16); // 0 0 | x db
110 const __m128i G0 = _mm_sub_epi8(E0, F0); // 0 0 | x b'
152 const __m128i F0 = _mm_and_si128(E0, mask); // 0 0 | 0 r'
154 const __m128i I = _mm_packs_epi32(F0, F1);
|
| /external/gemmlowp/internal/ |
| output.h | 312 typedef FixedPoint<DataType, 0> F0;
326 F0 fixedpoint_output = tanh(fixedpoint_input) * amplitude_normalized;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| MipsGenCallingConv.inc | 508 Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19
520 Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18
756 Mips::F0, Mips::F2
808 Mips::F0, Mips::F2
|
| /external/u-boot/lib/ |
| sha256.c | 90 #define F0(x,y,z) ((x & y) | (z & (x | y)))
101 temp2 = S2(a) + F0(a,b,c); \
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
| PlatformInfo.h | 331 F0 = 0,
382 GPIO_FUNC_NUM func; // Function Number (F0~F7)
|
| /external/libvpx/config/arm-neon/vpx_dsp/arm/ |
| loopfilter_4_neon.asm.S | 383 vld1.u8 {d21}, [r2] @ F0 F1 F2 F3 F4 F5 F6 F7
391 vtrn.8 q9, q10 @ q9 : 60 70 62 72 64 74 66 76 E0 F0 E2 F2 E4 F4 E6 F6
398 vtrn.16 q7, q9 @ q7 : 40 50 60 70 44 54 64 74 C0 D0 E0 F0 C4 D4 E4 F4
403 vtrn.32 q3, q7 @ q3 : 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0
|
| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| PPCDisassembler.cpp | 82 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
124 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
144 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
|
| /external/llvm/lib/Target/Sparc/ |
| LeonPasses.cpp | 52 for (int RegisterIndex = SP::F0; RegisterIndex <= SP::F31; ++RegisterIndex) {
120 // fstod %f20,%f0
122 // fmuld %f0,%f2,%f8
193 // create fstod %f20,%f0
203 // create fmuld %f0,%f2,%f8
232 // fstod %f20,%f0
234 // fmuld %f0,%f2,%f8
304 // create fstod %f20,%f0
314 // create fmuld %f0,%f2,%f8
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/Disassembler/ |
| PPCDisassembler.cpp | 82 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
135 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
155 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
|
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 112 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
391 unsigned regIdx = Reg - Sparc::F0;
405 regIdx = Reg - Sparc::F0;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 137 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
419 unsigned regIdx = Reg - Sparc::F0;
433 regIdx = Reg - Sparc::F0;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 54 case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64:
|
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/ |
| Flat32.S | 55 .equ HOST_BRIDGE_PFA, (0x0000) # B0:D0:F0 (Host Bridge)
56 .equ ILB_PFA, (0x00F8) # B0:D31:F0 (Legacy Block)
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/ |
| Platform.c | 70 GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,TRISTS ,NA ,F0 , , ,NONE ,0x47),
71 GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_resi_trans.s | 548 @ Calculating F0, F2, F4 and F6
583 VSHLL.S16 q12,d4,#6 @ q12 = F0[0] = 64*(C0 + C1 + C2 + C3 + C4 + C5 + C6 + C7)
585 VSHLL.S16 q2,d5,#6 @ q2 = F0[1] = 64*(C0 + C1 + C2 + C3 + C4 + C5 + C6 + C7)
590 VST1.64 {d24,d25},[r2]! @ Row 1 of transform stage 1 F0[0] stored
591 VST1.64 {d4,d5},[r2],r4 @ Row 1 of transform stage 1 F0[1] stored
646 @ Transposing the 4 rows (F0, F1, F2, F3)
647 @ F0 = {q2,q12}, F1 = {q8,q1}, F2 = {q15,q14} and F3 = {q13,q11}
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_swtcl.c | 61 #define EMIT_ATTR( ATTR, STYLE, F0 ) \
66 fmt_0 |= F0; \
|
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_swtcl.c | 66 #define EMIT_ATTR( ATTR, STYLE, F0 ) \
71 fmt_0 |= F0; \
|
