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  /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/
PL180Mci.c 38 return ((MmioRead32 (MCI_POWER_CONTROL_REG) & MCI_POWER_ON) == MCI_POWER_ON);
55 return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_CARDIN);
63 return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_WPROT);
165 Status = MmioRead32 (MCI_STATUS_REG);
173 DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n", (Cmd & 0x3F), MmioRead32 (MCI_RESPONSE0_REG), Status));
176 //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n", (Cmd & 0x3F), MmioRead32 (MCI_RESPONSE0_REG), Status));
185 CmdCtrlReg = MmioRead32 (MCI_COMMAND_REG);
207 Buffer[0] = MmioRead32 (MCI_RESPONSE3_REG);
209 Buffer[0] = MmioRead32 (MCI_RESPONSE0_REG);
210 Buffer[1] = MmioRead32 (MCI_RESPONSE1_REG);
    [all...]
  /device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/GicV2/
ArmGicV2Lib.c 25 return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
ArmGicV2SecLib.c 39 CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
44 InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
53 InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
98 ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);
  /device/linaro/bootloader/edk2/ArmPlatformPkg/Library/SP804TimerLib/
SP804TimerLib.c 37 if ((MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) == 0) {
46 if ((MmioRead32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) == 0) {
100 StartTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG);
132 CurrentTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG);
148 CurrentTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG);
153 CurrentTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG);
210 Value = MmioRead32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CURRENT_REG);
  /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/
Wtf_Reg.h 79 wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
87 wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
95 wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
102 wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
  /device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/
ArmGicNonSecLib.c 35 if (MmioRead32 (GicDistributorBase + ARM_GIC_ICDDCR) & ARM_GIC_ICDDCR_ARE) {
ArmGicSecLib.c 40 InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
  /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL011Uart/
PL011Uart.c 84 HardwareFifoDepth = (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) \
202 if (((MmioRead32 (UartBase + UARTCR) & PL011_UARTCR_UARTEN) != 0) &&
203 (MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&
204 (MmioRead32 (UartBase + UARTIBRD) == Integer) &&
205 (MmioRead32 (UartBase + UARTFBRD) == Fractional)) {
211 while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0);
274 Bits = MmioRead32 (UartBase + UARTCR);
349 FlagRegister = MmioRead32 (UartBase + UARTFR);
350 ControlRegister = MmioRead32 (UartBase + UARTCR);
420 while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK));
    [all...]
  /device/linaro/bootloader/edk2/Omap35xxPkg/Library/Omap35xxTimerLib/
TimerLib.c 35 if ((MmioRead32 (TimerBaseAddress + GPTIMER_TCLR) & TCLR_ST_ON) == 0) {
93 StartTime = MmioRead32 (TimerCountRegister);
97 CurrentTime = MmioRead32 (TimerCountRegister);
112 return (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TCRR);
124 *StartValue = (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TLDR);
  /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/SP805WatchdogDxe/
SP805Watchdog.c 45 if( MmioRead32(SP805_WDOG_LOCK_REG) == SP805_WDOG_LOCK_IS_LOCKED ) {
63 if( MmioRead32(SP805_WDOG_LOCK_REG) == SP805_WDOG_LOCK_IS_UNLOCKED ) {
79 if ( (MmioRead32(SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_INTEN) != 0 ) {
96 if ( (MmioRead32(SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_INTEN) == 0 ) {
268 if ( (MmioRead32(SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_INTEN) == 0 ) {
275 ReturnValue = MultU64x32( MmioRead32(SP805_WDOG_LOAD_REG), 600 );
349 if ((MmioRead32(SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_RESEN) == 0) {
  /device/linaro/bootloader/edk2/Omap35xxPkg/MMCHSDxe/
MMCHS.c 106 while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS);
124 while ((MmioRead32 (MMCHS_PSTATE) & DATI_MASK) == DATI_NOT_ALLOWED);
147 MmcStatus = MmioRead32 (MMCHS_STAT);
155 while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
400 while (!(MmioRead32 (MMCHS_STAT) & CC));
410 while (!(MmioRead32 (MMCHS_STAT) & CC));
429 DEBUG ((EFI_D_INFO, "CMD0 response: %x\n", MmioRead32 (MMCHS_RSP10)));
435 DEBUG ((EFI_D_INFO, "CMD5 response: %x\n", MmioRead32 (MMCHS_RSP10)));
444 while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
452 Response = MmioRead32 (MMCHS_RSP10);
    [all...]
  /device/linaro/bootloader/edk2/Omap35xxPkg/MmcHostDxe/
MmcHostDxe.c 242 while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS);
311 //return (MmioRead32 (GPIO1_BASE + GPIO_DATAIN) & BIT23) == BIT23;
351 while ((MmioRead32 (MMCHS_PSTATE) & DATI_MASK) == DATI_NOT_ALLOWED);
375 MmcStatus = MmioRead32 (MMCHS_STAT);
383 while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
432 while ((MmioRead32 (MMCHS_SYSSTATUS) & RESETDONE_MASK) != RESETDONE);
437 while ((MmioRead32 (MMCHS_SYSCTL) & SRA) != 0x0);
461 while ((MmioRead32 (MMCHS_HCTL) & SDBP_MASK) != SDBP_ON);
470 while (!(MmioRead32 (MMCHS_STAT) & CC));
480 while (!(MmioRead32 (MMCHS_STAT) & CC));
    [all...]
  /device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb/
DebugCommunicationLibUsb.c 301 while ((MmioRead32((UINTN)&DebugPortRegister->ControlStatus) & (UINT32)BIT16) == 0) {
302 if ((MmioRead32((UINTN)&DebugPortRegister->ControlStatus) & (USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_ENABLE))
316 if ((MmioRead32((UINTN)&DebugPortRegister->ControlStatus)) & BIT6) {
323 if (((MmioRead32((UINTN)&DebugPortRegister->ControlStatus)) & 0xF) > USB_DEBUG_PORT_MAX_PACKET_SIZE) {
327 *Length = (UINT8)(MmioRead32((UINTN)&DebugPortRegister->ControlStatus) & 0xF);
402 while ((MmioRead32((UINTN)&DebugPortRegister->ControlStatus) & BIT16) == 0) {
403 if ((MmioRead32((UINTN)&DebugPortRegister->ControlStatus) & (USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_ENABLE))
417 if ((MmioRead32((UINTN)&DebugPortRegister->ControlStatus)) & BIT6) {
424 if (((MmioRead32((UINTN)&DebugPortRegister->ControlStatus)) & 0xF) > USB_DEBUG_PORT_MAX_PACKET_SIZE) {
563 if ((MmioRead32((UINTN)&UsbDebugPortRegister->ControlStatus) & (USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_ENABLE | USB (…)
    [all...]
  /device/linaro/bootloader/OpenPlatformPkg/Drivers/Spi/
MvSpiDxe.c 83 Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
101 Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
116 Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
129 Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
153 Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
161 Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
215 Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
228 if (MmioRead32 (SpiRegBase + SPI_INT_CAUSE_REG)) {
229 *DataInPtr = MmioRead32 (SpiRegBase + SPI_DATA_IN_REG);
  /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/
I2CLib.c 132 if (MmioRead32 (PciMmBase) != 0xFFFFFFFF) {
133 if((MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_STSCMD)& B_PCH_LPSS_I2C_STSCMD_MSE)) {
137 mLpssPciDeviceList[I2cControllerIndex + 1].Bar0=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR);
138 mLpssPciDeviceList[I2cControllerIndex + 1].Bar1=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR1);
188 PmcBase = MmioRead32 (PCI_D31F0_REG_BASE + R_PCH_LPC_PMC_BASE) & B_PCH_LPC_PMC_BASE_BAR;
189 if(MmioRead32(PmcBase+R_PCH_PMC_FUNC_DIS)&PmcFunctionDsiable[I2cControllerIndex]) {
194 DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C()------------I2cControllerIndex=%x,PMC=%x\n",I2cControllerIndex,MmioRead32(PmcBase+R_PCH_PMC_FUNC_DIS)));
210 if (MmioRead32 (PciMmBase) != 0xFFFFFFFF) {
211 if((MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_STSCMD)& B_PCH_LPSS_I2C_STSCMD_MSE)) {
215 mLpssPciDeviceList[I2cControllerIndex+1].Bar0=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR);
    [all...]
  /device/linaro/bootloader/OpenPlatformPkg/Drivers/Mmc/DwEmmcDxe/
DwEmmcDxe.c 125 Data = MmioRead32 (DWEMMC_CMD);
129 Data = MmioRead32 (DWEMMC_RINTSTS);
160 Data = MmioRead32 (DWEMMC_STATUS);
200 Data = MmioRead32 (DWEMMC_CTRL);
217 Data = MmioRead32 (DWEMMC_BMOD);
283 Data = MmioRead32 (DWEMMC_STATUS);
295 Data = MmioRead32 (DWEMMC_RINTSTS);
408 Buffer[0] = MmioRead32 (DWEMMC_RESP0);
410 Buffer[0] = MmioRead32 (DWEMMC_RESP0);
411 Buffer[1] = MmioRead32 (DWEMMC_RESP1);
    [all...]
  /device/linaro/bootloader/edk2/BeagleBoardPkg/Library/BeagleBoardLib/
BeagleBoard.c 47 OldPinDir = MmioRead32 (GPIO6_BASE + GPIO_OE);
49 Revision = MmioRead32 (GPIO6_BASE + GPIO_DATAIN);
  /device/linaro/bootloader/edk2/QuarkPlatformPkg/Library/PlatformHelperLib/
PlatformHelperLib.c 53 if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) == 0) {
56 if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR1) == 0) {
59 if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR2) == 0) {
78 if (RegVal == MmioRead32 (PchRootComplexBar + Offset)) {
116 if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {
120 if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {
124 if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {
159 RegVal = MmioRead32 (PchRootComplexBar + Offset);
  /device/linaro/bootloader/edk2/Omap35xxPkg/Library/OmapDmaLib/
OmapDmaLib.c 58 RegVal = MmioRead32 (DMA4_CSDP (Channel));
89 RegVal = MmioRead32 (DMA4_CCR (Channel));
158 Reg = MmioRead32 (DMA4_CSR(Channel));
  /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/
NorFlashJuno.c 45 if ((MmioRead32 (ARM_VE_SYS_FLASH) & 0x1) == 0) {
  /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/SP804TimerDxe/
SP804Timer.c 81 if (MmioRead32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_MSK_INT_STS_REG) != 0) {
155 if (MmioRead32(SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
160 if (MmioRead32(SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
165 if (MmioRead32(SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
  /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/PchPlatformLib/
PchPlatformLibrary.c 126 Identifiers = MmioRead32 (
  /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/
ExI.c 38 #define PchLpcPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
  /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseTimerLibLocalApic/
X86TimerLib.c 114 return MmioRead32 (ApicBase + 0x390);
269 *StartValue = MmioRead32 (ApicBase + 0x380);
  /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960Dxe/
HiKey960Dxe.c 158 Data = MmioRead32 (HKADC_DSP_START);
162 Value1 = (UINT16)MmioRead32 (HKADC_DSP_RD2_DATA);
163 Value0 = (UINT16)MmioRead32 (HKADC_DSP_RD3_DATA);
276 Data = MmioRead32 (PMU_REG_BASE + (0x79 << 2)) & 7;
283 Data = MmioRead32 (PMU_REG_BASE + (0x6b << 2)) & 7;
308 Data = MmioRead32 (CRG_REG_BASE + 0xb8);
314 Data = MmioRead32 (CRG_PERRSTSTAT4);
320 Data = MmioRead32 (CRG_REG_BASE + 0x48);
362 BootMode = MmioRead32 (SCTRL_BAK_DATA0) & BOOT_MODE_MASK;
599 if (MmioRead32 (ADB_REBOOT_ADDRESS) != mRebootReason) {
    [all...]

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