| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| PchAccess.h | 56 MmioRead32 (MmPciAddress (0, \
67 MmioRead32 ( \
181 #define PchLpcPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
284 #define PchSataPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
387 #define PchMmRcrb32(Register) MmioRead32 (PCH_RCRB_BASE + Register)
435 (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
442 (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
452 (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
462 (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyDxe/ |
| HiKeyDxe.c | 84 Val = MmioRead32 (PMUSSI_REG(0x1c)) | 0x40;
99 Data = MmioRead32 (AO_CTRL_BASE + SC_PW_MTCMOS_ACK_STAT0);
116 Data = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_RSTSTAT3);
300 if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) {
324 if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) {
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyUsbDxe/ |
| HiKeyUsbDxe.c | 111 Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CLKSTAT0);
119 Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_RSTSTAT0);
123 Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CTRL4);
139 Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5);
151 Data = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5);
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960UsbDxe/ |
| HiKey960UsbDxe.c | 62 Data = MmioRead32 (USB3OTG_PHY_CR_STS);
104 Data = MmioRead32 (USB3OTG_PHY_CR_STS);
136 Data = MmioRead32 (USB3OTG_PHY_CR_CTRL);
166 Data = MmioRead32 (USB3OTG_CTRL6);
173 MmioRead32 (USB3OTG_CTRL6)
|
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/MvMdioDxe/ |
| MvMdioDxe.c | 82 MdioReg = MmioRead32(MdioBase);
104 MdioReg = MmioRead32 (MdioBase);
161 *Data = MmioRead32 (MdioBase) & MVEBU_SMI_DATA_MASK;
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ |
| ArmVExpressSysConfig.c | 89 while ((MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_COMPLETE) == 0);
92 if(MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_ERROR) {
98 *Data = MmioRead32(ARM_VE_SYS_CFGDATA_REG);
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigRuntimeLib/ |
| ArmVExpressSysConfigRuntimeLib.c | 96 while ((MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_COMPLETE) == 0);
99 if(MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_ERROR) {
105 *Data = MmioRead32(ARM_VE_SYS_CFGDATA_REG);
|
| /device/linaro/bootloader/edk2/MdePkg/Library/SecPeiDxeTimerLibCpu/ |
| X86TimerLib.c | 80 ASSERT ((MmioRead32 (ApicBase + APIC_SVR) & BIT8) != 0);
118 return MmioRead32 (ApicBase + APIC_TMCCT);
134 return MmioRead32 (ApicBase + APIC_TMICT);
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/ |
| CTA9x4Sec.c | 50 if (MmioRead32(ARM_VE_SYS_CFGRW1_REG) & ARM_VE_CFGRW1_TZASC_EN_BIT_MASK) {
170 Value = MmioRead32 (ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
|
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Block/DwUfsHcDxe/ |
| DwUfsHcDxe.c | 68 Data = MmioRead32 (RegBase + UFS_HC_STATUS_OFFSET);
78 Data = MmioRead32 (RegBase + UFS_HC_IS_OFFSET);
84 Data = MmioRead32 (RegBase + UFS_HC_UCMD_ARG2_OFFSET);
102 Data = MmioRead32 (RegBase + UFS_HC_STATUS_OFFSET);
112 Data = MmioRead32 (RegBase + UFS_HC_IS_OFFSET);
118 Data = MmioRead32 (RegBase + UFS_HC_UCMD_ARG2_OFFSET);
122 *Value = MmioRead32 (RegBase + UFS_HC_UCMD_ARG3_OFFSET);
364 *((UINT32 *)Buffer + Index) = MmioRead32 (Private->RegBase + Offset);
494 Data = MmioRead32 (Private->RegBase + UFS_HC_AHIT_OFFSET);
583 Data = MmioRead32(Private->RegBase + UFS_HC_IS_OFFSET);
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/D03/Library/OemMiscLib2P/ |
| OemMiscLib2PHi1610.c | 114 Tmp = MmioRead32(0x602E0050);
|
| /device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/ |
| ArmGicLib.c | 94 return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR);
103 return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
272 Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);
280 Interrupts = MmioRead32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * RegOffset));
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmJunoPkg/Include/ |
| ArmPlatform.h | 107 SysId = MmioRead32 (ARM_VE_BOARD_PERIPH_BASE+ARM_VE_BOARD_SYS_ID); \
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/AArch64/ |
| ArmFvpDxeAArch64.c | 62 SysId = MmioRead32 (ARM_VE_SYS_ID_REG);
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/Arm/ |
| ArmFvpDxeArm.c | 60 SysId = MmioRead32 (ARM_VE_SYS_ID_REG);
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/ |
| NorFlashArmVExpress.c | 61 if ((MmioRead32 (ARM_VE_SYS_FLASH) & 0x1) == 0) {
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Marvell/Library/UtmiPhyLib/ |
| UtmiPhyLib.c | 54 RegData = MmioRead32 (Addr);
70 DEBUG((DEBUG_INFO, "old value = %10x ==>\n", MmioRead32 (Addr)));
72 DEBUG((DEBUG_INFO, "new value %10x\n", MmioRead32 (Addr)));
211 Data = MmioRead32 (UtmiBaseAddr + UTMI_CALIB_CTRL_REG);
220 Data = MmioRead32 (UtmiBaseAddr + UTMI_PLL_CTRL_REG);
|
| /device/linaro/bootloader/edk2/SecurityPkg/Library/Tpm2DeviceLibDTpm/ |
| Tpm2Ptp.c | 94 RegRead = MmioRead32 ((UINTN)Register);
369 InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
370 InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
408 InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
409 InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
|
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Pp2Dxe/ |
| Pp2Dxe.h | 384 return MmioRead32 (Priv->Base + Offset);
396 return MmioRead32 (Priv->Rfu1Base + Offset);
421 return MmioRead32 (Priv->SmiBase + Offset);
459 return MmioRead32 (Port->Priv->Base + Offset);
484 return MmioRead32 (Port->GmacBase + Offset);
509 return MmioRead32 (Port->XlgBase + Offset);
|
| /device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/GicV3/ |
| ArmGicV3Dxe.c | 285 CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);
299 if ((MmioRead32 (mGicDistributorBase + ARM_GIC_ICDDCR) & ARM_GIC_ICDDCR_DS) != 0) {
|
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseIoLibIntrinsic/ |
| IoHighLevel.c | [all...] |
| IoLibIpf.c | 113 return MmioRead32 (Address);
331 MmioRead32 (
|
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeIoLibCpuIo/ |
| IoHighLevel.c | [all...] |
| /device/linaro/bootloader/edk2/IntelFrameworkPkg/Library/DxeIoLibCpuIo/ |
| IoHighLevel.c | [all...] |
| /device/linaro/bootloader/edk2/MdePkg/Library/BaseIoLibIntrinsic/ |
| IoHighLevel.c | [all...] |
