| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeIoLibCpuIo/ |
| IoLib.c | 536 MmioWrite32 (
|
| /device/linaro/bootloader/edk2/EmbeddedPkg/Ebl/ |
| HwDebug.c | 118 MmioWrite32 (Address, Data);
|
| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Universal/CpuIoDxe/ |
| CpuIo.c | 339 MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
|
| /device/linaro/bootloader/edk2/IntelFrameworkPkg/Library/DxeIoLibCpuIo/ |
| IoLib.c | 554 MmioWrite32 (
|
| IoLibMmioBuffer.c | 355 MmioWrite32 (StartAddress, *(Buffer++));
|
| /device/linaro/bootloader/edk2/MdePkg/Library/BaseIoLibIntrinsic/ |
| IoLibMmioBuffer.c | 350 MmioWrite32 (StartAddress, *(Buffer++));
|
| /device/linaro/bootloader/edk2/MdePkg/Library/DxeIoLibCpuIo2/ |
| IoLib.c | 549 MmioWrite32 (
|
| IoLibMmioBuffer.c | 352 MmioWrite32 (StartAddress, *(Buffer++));
|
| /device/linaro/bootloader/edk2/MdePkg/Library/DxeIoLibEsal/ |
| IoLib.c | 541 MmioWrite32 (
|
| IoLibMmioBuffer.c | 350 MmioWrite32 (StartAddress, *(Buffer++));
|
| /device/linaro/bootloader/edk2/MdePkg/Library/PeiIoLibCpuIo/ |
| IoLib.c | 487 MmioWrite32 (
|
| IoLibMmioBuffer.c | 357 MmioWrite32 (StartAddress, *(Buffer++));
|
| /device/linaro/bootloader/edk2/MdePkg/Library/SmmIoLibSmmCpuIo2/ |
| IoLibMmioBuffer.c | 355 MmioWrite32 (StartAddress, *(Buffer++));
|
| /device/linaro/bootloader/edk2/UefiCpuPkg/CpuIo2Dxe/ |
| CpuIo2Dxe.c | 340 MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
|
| /device/linaro/bootloader/edk2/UefiCpuPkg/CpuIo2Smm/ |
| CpuIo2Smm.c | 248 MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/NorFlashDxe/ |
| NorFlashHw.c | 64 MmioWrite32 (FlashAddr, InputData);
346 MmioWrite32 (dwCommAddr, *pdwData);
|
| /device/linaro/bootloader/edk2/SecurityPkg/Tcg/Tcg2Config/ |
| Tcg2ConfigImpl.c | 189 MmioWrite32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId, InterfaceId.Uint32);
196 MmioWrite32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId, InterfaceId.Uint32);
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Marvell/Library/UtmiPhyLib/ |
| UtmiPhyLib.c | 57 MmioWrite32 (Addr, RegData);
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/NorFlashDxe/ |
| NorFlashDxe.h | 52 #define SEND_NOR_COMMAND(BaseAddr,Offset,Cmd) MmioWrite32 (CREATE_NOR_ADDRESS(BaseAddr,Offset), CREATE_DUAL_CMD(Cmd))
|
| /device/linaro/bootloader/edk2/SecurityPkg/Library/Tpm12DeviceLibDTpm/ |
| Tpm12Tis.c | 511 MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
|
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Compatibility/MpServicesOnFrameworkMpServicesThunk/ |
| MpServicesOnFrameworkMpServicesThunk.c | 617 MmioWrite32 (ApicBase + APIC_REGISTER_TIMER_DIVIDE, CurrentTimerDivide);
618 MmioWrite32 (ApicBase + APIC_REGISTER_TIMER_INIT_COUNT, CurrentTimerValue);
619 MmioWrite32 (ApicBase + APIC_REGISTER_LVT_TIMER, CurrentTimerRegister);
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| XhcPeim.c | 109 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data);
255 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset, Data);
299 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset, Data);
[all...] |
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/ |
| Platform.c | 348 MmioWrite32(mmio_padval, pad_val.dw);
417 MmioWrite32 (mmio_conf0, conf0_val.dw);
615 MmioWrite32(mmio_reg, Gpio_Conf_Data[index].val);
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Library/PiDxeS3BootScriptLib/ |
| BootScriptExecute.c | 579 MmioWrite32 ((UINTN) Address, *In.Uint32);
583 MmioWrite32 ((UINTN) OriginalAddress, *In.Uint32);
587 MmioWrite32 ((UINTN) Address, *OriginalIn.Uint32);
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/SdMmc/XenonDxe/ |
| XenonSdhci.c | 542 MmioWrite32 (SDHC_DAT_BUF_PORT_ADDR, *(UINT32 *)Offs);
|
