| /device/linaro/bootloader/edk2/ArmVirtPkg/Library/BaseCachingPciExpressLib/ |
| PciExpressLib.c | 903 return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciExpressLib/ |
| PciLib.c | 854 return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
[all...] |
| /device/linaro/bootloader/edk2/MdePkg/Library/BasePciExpressLib/ |
| PciExpressLib.c | 893 return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
[all...] |
| /device/linaro/bootloader/edk2/MdePkg/Library/SmmPciExpressLib/ |
| PciExpressLib.c | 905 return MmioWrite32 (GetPciExpressAddress (Address), Value);
[all...] |
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/NorFlashDxe/ |
| NorFlashDxe.c | 399 MmioWrite32 (WordAddress, WriteData);
528 MmioWrite32 ((UINTN)Data, *Buffer);
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/ |
| VirtualEhciPciIo.c | 214 MmioWrite32(mUsbMemBase + Offset + i * 4, *((UINT32 *)Buffer + i));
|
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/I2c/MvI2cDxe/ |
| MvI2cDxe.c | 93 return MmioWrite32 (I2cMasterContext->BaseAddress + off, Value);
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/ |
| HiKeyFastbootDxe.c | 596 MmioWrite32 (ADB_REBOOT_ADDRESS, ADB_REBOOT_BOOTLOADER);
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960FastbootDxe/ |
| HiKey960FastbootDxe.c | 645 MmioWrite32 (ADB_REBOOT_ADDRESS, ADB_REBOOT_BOOTLOADER);
|
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/Library/ |
| EdkIIGlueIoLib.h | [all...] |
| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| Lan9118DxeUtil.c | 161 MmioWrite32(Address, Value);
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/EhciPei/ |
| EhcPeim.c | 82 MmioWrite32(Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data);
[all...] |
| /device/linaro/bootloader/edk2/MdePkg/Include/Library/ |
| IoLib.h | [all...] |
| /device/linaro/bootloader/edk2/MdePkg/Library/DxeRuntimePciExpressLib/ |
| PciExpressLib.c | [all...] |
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Spi/Common/ |
| SpiCommon.c | 765 MmioWrite32 (
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/ |
| OhciReg.c | 59 MmioWrite32(Ohc->UsbHostControllerBaseAddress + Offset, *Value);
|
| /device/linaro/bootloader/edk2/ShellPkg/Library/UefiShellDebug1CommandsLib/ |
| Mm.c | 264 MmioWrite32 ((UINTN) Address, *(UINT32 *) Buffer);
|
| /device/linaro/bootloader/edk2/UefiCpuPkg/Library/BaseXApicLib/ |
| BaseXApicLib.c | 169 MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformInitPei/ |
| PchInitPeim.c | 704 MmioWrite32 (SPI_BASE_ADDRESS + R_PCH_SPI_FDOC, V_PCH_SPI_FDOC_FDSS_FSDM);
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/SasV1Dxe/ |
| SasV1Dxe.c | 36 #define WRITE_REG32(Base, Offset, Val) MmioWrite32 ((Base) + (Offset), (Val))
39 #define PHY_WRITE_REG32(Base, Offset, phy, Val) MmioWrite32 ((Base) + (Offset) + 0x400 * (phy), (Val))
[all...] |
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformSetupDxe/ |
| SetupInfoRecords.c | [all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/ |
| if_mskreg.h | [all...] |
| /device/linaro/bootloader/edk2/MdePkg/Library/BaseS3IoLib/ |
| S3IoLib.c | [all...] |
| /device/linaro/bootloader/edk2/SecurityPkg/Tcg/Opal/OpalPasswordSmm/ |
| OpalAhciMode.c | 93 MmioWrite32 (mAhciBar + Offset, Data);
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/ |
| EmmcHci.c | 70 MmioWrite32 (Address, *(UINT32*)Data);
[all...] |
