| /device/linaro/bootloader/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/ |
| DefaultExceptionHandler.c | 195 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"\n%a Exception PC at 0x%08x CPSR 0x%08x ",
196 gExceptionTypeString[ExceptionType], SystemContext.SystemContextArm->PC, SystemContext.SystemContextArm->CPSR);
213 Pdb = GetImageName (SystemContext.SystemContextArm->PC, &ImageBase, &PeCoffSizeOfHeader);
214 Offset = SystemContext.SystemContextArm->PC - ImageBase;
229 DisAsm = (UINT8 *)(UINTN)SystemContext.SystemContextArm->PC;
239 // advance PC past the faulting instruction
240 PcAdjust = (UINTN)DisAsm - SystemContext.SystemContextArm->PC;
252 DEBUG ((EFI_D_ERROR, " R12 0x%08x SP 0x%08x LR 0x%08x PC 0x%08x\n", SystemContext.SystemContextArm->R12, SystemContext.SystemContextArm->SP, SystemContext.SystemContextArm->LR, SystemContext.SystemContextArm->PC));
274 // If some one is stepping past the exception handler adjust the PC to point to the next instruction
[all...] |
| /external/u-boot/board/bachmann/ot1200/ |
| ot1200.c | 122 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
127 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
128 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
132 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
133 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
141 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
142 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
146 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
147 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
|
| /external/llvm/test/ExecutionEngine/RuntimeDyld/X86/ |
| MachO_x86-64_PIC_relocations.s | 13 # Test PC-rel branch.
18 # Test PC-rel signed.
23 # Test PC-rel GOT relocation.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/ExecutionEngine/RuntimeDyld/X86/ |
| MachO_x86-64_PIC_relocations.s | 14 # Test PC-rel branch.
19 # Test PC-rel signed.
24 # Test PC-rel GOT relocation.
|
| ELF_x86-64_PIC-small-relocations.s | 13 # Test PC-rel branch.
|
| /art/runtime/arch/arm/ |
| registers_arm.h | 49 PC = 15,
|
| /bionic/libc/kernel/uapi/asm-mips/asm/ |
| ptrace.h | 23 #define PC 64
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmSoftFloatLib/Arm/ |
| __aeabi_cdcmp.asm | 39 POPEQ {R0 - R3, IP, PC}
45 POP {R0 - R3, IP, PC}
|
| __aeabi_cfcmp.asm | 35 POPEQ {R0 - R3, IP, PC}
41 POP {R0 - R3, IP, PC}
|
| /external/blktrace/ |
| act_mask.c | 25 DECLARE_MASK_MAP(PC),
|
| /external/kernel-headers/original/uapi/asm-mips/asm/ |
| ptrace.h | 17 #define PC 64
|
| /external/llvm/lib/Target/MSP430/MCTargetDesc/ |
| MSP430MCTargetDesc.cpp | 41 InitMSP430MCRegisterInfo(X, MSP430::PC);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm-c/ |
| Disassembler.h | 95 * instruction is at the address specified by the PC parameter. If a valid
102 uint64_t BytesSize, uint64_t PC,
|
| DisassemblerTypes.h | 31 * is at the PC parameter. For some instruction sets, there can be more than
42 typedef int (*LLVMOpInfoCallback)(void *DisInfo, uint64_t PC,
56 * including any PC adjustment, is passed in to the call back in the Value
102 * disassembler for things like adding a comment for a PC plus a constant
107 * instruction is passed indirectly as is the PC of the instruction in
125 /* The input reference is from a PC relative load instruction. */
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| ARCBranchFinalize.cpp | 152 unsigned PC = 0;
155 BlockToPCMap.insert(std::make_pair(&MBB, PC));
165 BranchToPCList.emplace_back(&MI, PC);
167 PC += Size;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/MCTargetDesc/ |
| MSP430MCTargetDesc.cpp | 41 InitMSP430MCRegisterInfo(X, MSP430::PC);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/ |
| Nios2RegisterInfo.cpp | 40 Nios2::RA, Nios2::PC, Nios2::GP};
|
| /external/u-boot/board/barco/platinum/ |
| platinum_titanium.c | 97 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
98 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
110 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
111 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
|
| /external/llvm/include/llvm-c/ |
| Disassembler.h | 43 * is at the PC parameter. For some instruction sets, there can be more than
54 typedef int (*LLVMOpInfoCallback)(void *DisInfo, uint64_t PC,
68 * including any PC adjustment, is passed in to the call back in the Value
114 * disassembler for things like adding a comment for a PC plus a constant
119 * instruction is passed indirectly as is the PC of the instruction in
137 /* The input reference is from a PC relative load instruction. */
240 * instruction is at the address specified by the PC parameter. If a valid
247 uint64_t BytesSize, uint64_t PC,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/ |
| MCAsmInfo.cpp | 96 const MCExpr *PC = MCSymbolRefExpr::create(PCSym, Context);
97 return MCBinaryExpr::createSub(Res, PC, Context);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCAsmInfo.cpp | 56 // is an indirect pc-relative reference. The default implementation
64 const MCExpr *PC = MCSymbolRefExpr::create(PCSym, Context);
65 return MCBinaryExpr::createSub(Res, PC, Context);
|
| /external/python/cpython2/PC/VS7.1/ |
| _ssl.mak | 15 INCLUDES=-I ../../Include -I ../../PC -I $(SSL_DIR)/inc32
26 _ssl$(SUFFIX): $(SSL_SOURCE) $(SSL_LIB_DIR)/libeay32.lib $(SSL_LIB_DIR)/ssleay32.lib ../../PC/*.h ../../Include/*.h
33 _hashlib$(SUFFIX): $(HASH_SOURCE) $(SSL_LIB_DIR)/libeay32.lib ../../PC/*.h ../../Include/*.h
|
| /external/u-boot/board/gateworks/gw_ventana/ |
| common.c | 91 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
92 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
96 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
97 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
103 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
104 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
108 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
109 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
117 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
118 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
[all...] |
| /device/linaro/bootloader/edk2/EmbeddedPkg/Library/GdbDebugAgent/Arm/ |
| ExceptionSupport.ARMv6.S | 38 PC 0x3c
99 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
111 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
123 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
135 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
146 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
158 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
206 ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd
213 addne R5, R5, #2 @ PC += 2@
218 str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
[all...] |
| /external/libcxx/test/std/containers/associative/map/map.ops/ |
| find.pass.cpp | 227 typedef PrivateConstructor PC;
228 typedef std::map<PC, double, std::less<>> M;
232 m [ PC::make(5) ] = 5;
233 m [ PC::make(6) ] = 6;
234 m [ PC::make(7) ] = 7;
235 m [ PC::make(8) ] = 8;
236 m [ PC::make(9) ] = 9;
237 m [ PC::make(10) ] = 10;
238 m [ PC::make(11) ] = 11;
239 m [ PC::make(12) ] = 12
[all...] |
