| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | [all...] |
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 186 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
474 PredReg = MCI.getOperand(1).getReg(); // P0
476 Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | [all...] |
| HexagonHardwareLoops.cpp | 615 unsigned PredReg, PredPos, PredRegFlags;
616 if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags))
618 MachineInstr *CondI = MRI->getVRegDef(PredReg);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | [all...] |
| HexagonHardwareLoops.cpp | 648 unsigned PredReg, PredPos, PredRegFlags;
649 if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags))
651 MachineInstr *CondI = MRI->getVRegDef(PredReg);
[all...] |
