| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86RegisterInfo.cpp | 56 ? X86::RIP : X86::EIP,
400 Reserved.set(X86::RIP);
|
| X86ISelDAGToDAG.cpp | 89 /// isRIPRelative - Return true if this addressing mode is already RIP
95 return RegNode->getReg() == X86::RIP;
238 // These are 32-bit even in 64-bit mode since RIP relative offset
622 // Handle X86-64 rip-relative addresses. We check this before checking direct
623 // folding because RIP is preferable to non-RIP accesses.
629 // Base and index reg must be 0 in order to use %rip as base and lowering
630 // must allow RIP.
661 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
667 // mode, this results in a non-RIP-relative computation
[all...] |
| X86MCInstLower.cpp | 552 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
|
| X86InstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
| ObjCARC.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86InstructionSelector.cpp | 596 // Use rip-relative addressing.
598 AM.Base.Reg = X86::RIP;
[all...] |
| X86FastISel.cpp | 745 // RIP-relative addresses can't have additional register operands, so if
766 // Use rip-relative addressing if we can. Above we verified that the
769 AM.Base.Reg = X86::RIP;
798 StubAM.Base.Reg = X86::RIP;
[all...] |
| X86MCInstLower.cpp | 764 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
[all...] |
| X86FrameLowering.cpp | 188 if (!Uses.count(CS) && CS != X86::RIP)
[all...] |
| X86ISelDAGToDAG.cpp | 89 /// Return true if this addressing mode is already RIP-relative.
94 return RegNode->getReg() == X86::RIP;
262 // These are 32-bit even in 64-bit mode since RIP-relative offset
[all...] |
| X86InstrInfo.cpp | 545 if (BaseReg == 0 || BaseReg == X86::RIP)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 718 // RIP-relative addresses can't have additional register operands, so if
739 // Use rip-relative addressing if we can. Above we verified that the
742 AM.Base.Reg = X86::RIP;
771 StubAM.Base.Reg = X86::RIP;
[all...] |
| X86FrameLowering.cpp | 189 if (!Uses.count(CS) && CS != X86::RIP)
[all...] |
| X86ISelDAGToDAG.cpp | 89 /// Return true if this addressing mode is already RIP-relative.
94 return RegNode->getReg() == X86::RIP;
255 // These are 32-bit even in 64-bit mode since RIP-relative offset
749 // Handle X86-64 rip-relative addresses. We check this before checking direct
750 // folding because RIP is preferable to non-RIP accesses.
756 // Base and index reg must be 0 in order to use %rip as base.
796 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
802 // mode, this only applies to a non-RIP-relative computation.
806 "RIP-relative addressing already handled")
[all...] |
| X86MCInstLower.cpp | 729 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
[all...] |
| X86InstrInfo.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 252 // Handle %rip relative addressing.
253 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
254 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode");
255 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
266 // rip-relative addressing is actually relative to the *next* instruction.
281 // If no BaseReg, issue a RIP relative instruction only if the MCE can
292 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 305 /// referenced by a load instruction with the base register that is the rip.
[all...] |
| /external/syzkaller/pkg/report/ |
| linux.go | [all...] |
| /art/compiler/utils/x86_64/ |
| assembler_x86_64.h | 250 // If no_rip is true then the Absolute address isn't RIP relative.
258 // RIP addressing is done using RBP as the base register.
259 // The value in RBP isn't used. Instead the offset is added to RIP.
266 // An RIP relative address that will be fixed up later.
267 static Address RIP(AssemblerFixup* fixup) {
269 // RIP addressing is done using RBP as the base register.
270 // The value in RBP isn't used. Instead the offset is added to RIP.
277 // If no_rip is true then the Absolute address isn't RIP relative.
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 288 /// referenced by a load instruction with the base register that is the rip.
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 361 // Handle %rip relative addressing.
362 if (BaseReg == X86::RIP ||
363 BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
364 assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode");
365 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
395 // rip-relative addressing is actually relative to the *next* instruction.
470 // If no BaseReg, issue a RIP relative instruction only if the MCE can
481 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 358 // leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15
390 // Handle %rip relative addressing.
391 if (BaseReg == X86::RIP ||
392 BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
393 assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode");
394 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
425 // rip-relative addressing is actually relative to the *next* instruction.
430 // Note: rip-relative addressing using immediate displacement values should
504 // If no BaseReg, issue a RIP relative instruction only if the MCE can
515 // byte to emit an addr that is just 'disp32' (the non-RIP relative form)
[all...] |
| /art/compiler/optimizing/ |
| code_generator_x86_64.cc | [all...] |
